diff options
| author | Markos Chandras <markos.chandras@imgtec.com> | 2013-09-19 18:18:41 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-01-22 20:18:56 +0100 |
| commit | 175cba8c7457a4d1c331a45323600368ba977fbf (patch) | |
| tree | b38fcbe0290b5f68f8dd168ed7b563d9d51a5877 /arch/mips | |
| parent | 40149889ce4d3c99fdbea6b6ca803bb872daebb5 (diff) | |
| download | linux-stable-175cba8c7457a4d1c331a45323600368ba977fbf.tar.gz linux-stable-175cba8c7457a4d1c331a45323600368ba977fbf.tar.bz2 linux-stable-175cba8c7457a4d1c331a45323600368ba977fbf.zip | |
MIPS: mm: c-r4k: Panic if IL or DL fields have a reserved value
According to MIPS32 and MIPS64 PRA documents,
a value of 7 in IL and DL fields is marked as "Reserved"
so panic if the core uses this value in the config1 register.
Also simplify the code a little bit.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5861/
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 62ffd20ea869..a4e1a692e45a 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1013,10 +1013,14 @@ static void probe_pcache(void) */ config1 = read_c0_config1(); - if ((lsize = ((config1 >> 19) & 7))) - c->icache.linesz = 2 << lsize; - else - c->icache.linesz = lsize; + lsize = (config1 >> 19) & 7; + + /* IL == 7 is reserved */ + if (lsize == 7) + panic("Invalid icache line size"); + + c->icache.linesz = lsize ? 2 << lsize : 0; + c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); c->icache.ways = 1 + ((config1 >> 16) & 7); @@ -1033,10 +1037,14 @@ static void probe_pcache(void) */ c->dcache.flags = 0; - if ((lsize = ((config1 >> 10) & 7))) - c->dcache.linesz = 2 << lsize; - else - c->dcache.linesz= lsize; + lsize = (config1 >> 10) & 7; + + /* DL == 7 is reserved */ + if (lsize == 7) + panic("Invalid dcache line size"); + + c->dcache.linesz = lsize ? 2 << lsize : 0; + c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); c->dcache.ways = 1 + ((config1 >> 7) & 7); |