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| author | Phil Edworthy <phil.edworthy@renesas.com> | 2014-06-13 10:37:15 +0100 |
|---|---|---|
| committer | Stephane Desneux <stephane.desneux@open.eurogiciel.org> | 2015-02-04 11:16:04 +0100 |
| commit | b3cb34a7aedc75916b945eb0aac6ad73b55d7c93 (patch) | |
| tree | 207bca60844e98fda2e854a4befc3b2c88e632b1 /arch/arm/boot/dts | |
| parent | fd4923517c6507822504becf28c84a944f5e9c09 (diff) | |
| download | linux-stable-b3cb34a7aedc75916b945eb0aac6ad73b55d7c93.tar.gz linux-stable-b3cb34a7aedc75916b945eb0aac6ad73b55d7c93.tar.bz2 linux-stable-b3cb34a7aedc75916b945eb0aac6ad73b55d7c93.zip | |
ARM: shmobile: r8a7790: Add PCIEC clock device tree node
This patch adds the device tree clock node for the PCIe Controller
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit ecafea8cd261833d7bb857aad76cf2e721821e88)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/r8a7790.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 29907c9d8e5b..9df57122e9c0 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -765,17 +765,17 @@ reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, - <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; + <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 - R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 + R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 >; clock-output-names = "iic2", "tpu0", "mmcif1", "sdhi3", "sdhi2", "sdhi1", "sdhi0", "mmcif0", - "iic0", "iic1", "ssusb", "cmt1"; + "iic0", "pciec", "iic1", "ssusb", "cmt1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |