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| author | Stephen Boyd <sboyd@codeaurora.org> | 2014-01-15 10:47:22 -0800 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-01-16 12:00:57 -0800 |
| commit | 3fa2252b7a78a8057017471a28f47b306e95ee26 (patch) | |
| tree | e3cf04e4099a9414b15d27f6428f7726f29d7a05 /Documentation/clk.txt | |
| parent | d0d44dd4ac58bc547646a9d0e65b4648f97cb533 (diff) | |
| download | linux-stable-3fa2252b7a78a8057017471a28f47b306e95ee26.tar.gz linux-stable-3fa2252b7a78a8057017471a28f47b306e95ee26.tar.bz2 linux-stable-3fa2252b7a78a8057017471a28f47b306e95ee26.zip | |
clk: Add set_rate_and_parent() op
Some of Qualcomm's clocks can change their parent and rate at the
same time with a single register write. Add support for this
hardware to the common clock framework by adding a new
set_rate_and_parent() op. When the clock framework determines
that both the parent and the rate are going to change during
clk_set_rate() it will call the .set_rate_and_parent() op if
available and fall back to calling .set_parent() followed by
.set_rate() otherwise.
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'Documentation/clk.txt')
| -rw-r--r-- | Documentation/clk.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/clk.txt b/Documentation/clk.txt index eb20198783cd..699ef2a323b1 100644 --- a/Documentation/clk.txt +++ b/Documentation/clk.txt @@ -77,6 +77,9 @@ the operations defined in clk.h: int (*set_parent)(struct clk_hw *hw, u8 index); u8 (*get_parent)(struct clk_hw *hw); int (*set_rate)(struct clk_hw *hw, unsigned long); + int (*set_rate_and_parent)(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, u8 index); unsigned long (*recalc_accuracy)(struct clk_hw *hw, unsigned long parent_accuracy); void (*init)(struct clk_hw *hw); |