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authorCarlo Caione <carlo@endlessm.com>2015-06-01 13:13:53 +0200
committerStephen Boyd <sboyd@codeaurora.org>2015-06-05 17:22:08 -0700
commit7a29a869434e8b7a71972227f0920e2f8ea777bd (patch)
treed0f3acdcf9d0f11dc7139c26ffca5892010dd957 /include/dt-bindings
parentb787f68c36d49bb1d9236f403813641efa74a031 (diff)
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clk: meson: Add support for Meson clock controller
This patchset adds the infrastructure for registering and managing the core clocks found on Amlogic MesonX SoCs. In particular: - PLLs - CPU clock - Fixed rate clocks, fixed factor clocks, ... Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/meson8b-clkc.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
new file mode 100644
index 000000000000..bd2720d58e0c
--- /dev/null
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -0,0 +1,25 @@
+/*
+ * Meson8b clock tree IDs
+ */
+
+#ifndef __MESON8B_CLKC_H
+#define __MESON8B_CLKC_H
+
+#define CLKID_UNUSED 0
+#define CLKID_XTAL 1
+#define CLKID_PLL_FIXED 2
+#define CLKID_PLL_VID 3
+#define CLKID_PLL_SYS 4
+#define CLKID_FCLK_DIV2 5
+#define CLKID_FCLK_DIV3 6
+#define CLKID_FCLK_DIV4 7
+#define CLKID_FCLK_DIV5 8
+#define CLKID_FCLK_DIV7 9
+#define CLKID_CLK81 10
+#define CLKID_MALI 11
+#define CLKID_CPUCLK 12
+#define CLKID_ZERO 13
+
+#define CLK_NR_CLKS (CLKID_ZERO + 1)
+
+#endif /* __MESON8B_CLKC_H */