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| author | Chen Yucong <slaoub@gmail.com> | 2014-11-18 10:09:19 +0800 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2014-11-19 10:55:43 -0800 |
| commit | e3480271f59253cb60d030aa5e615bf00b731fea (patch) | |
| tree | 3a75fe5ed4dfa7788bfe82893ba6e8699794580a /drivers/edac | |
| parent | 8dcf32ea220d87ca517e164de85d336480c9d172 (diff) | |
| download | linux-rpi3-e3480271f59253cb60d030aa5e615bf00b731fea.tar.gz linux-rpi3-e3480271f59253cb60d030aa5e615bf00b731fea.tar.bz2 linux-rpi3-e3480271f59253cb60d030aa5e615bf00b731fea.zip | |
x86, mce, severity: Extend the the mce_severity mechanism to handle UCNA/DEFERRED error
Until now, the mce_severity mechanism can only identify the severity
of UCNA error as MCE_KEEP_SEVERITY. Meanwhile, it is not able to filter
out DEFERRED error for AMD platform.
This patch extends the mce_severity mechanism for handling
UCNA/DEFERRED error. In order to do this, the patch introduces a new
severity level - MCE_UCNA/DEFERRED_SEVERITY.
In addition, mce_severity is specific to machine check exception,
and it will check MCIP/EIPV/RIPV bits. In order to use mce_severity
mechanism in non-exception context, the patch also introduces a new
argument (is_excp) for mce_severity. `is_excp' is used to explicitly
specify the calling context of mce_severity.
Reviewed-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Signed-off-by: Chen Yucong <slaoub@gmail.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'drivers/edac')
| -rw-r--r-- | drivers/edac/mce_amd.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/edac/mce_amd.h b/drivers/edac/mce_amd.h index 51b7e3a36e37..c2359a1ea6b3 100644 --- a/drivers/edac/mce_amd.h +++ b/drivers/edac/mce_amd.h @@ -32,9 +32,6 @@ #define R4(x) (((x) >> 4) & 0xf) #define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!") -#define MCI_STATUS_DEFERRED BIT_64(44) -#define MCI_STATUS_POISON BIT_64(43) - extern const char * const pp_msgs[]; enum tt_ids { |