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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-04-15 12:11:21 +0200 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2016-04-18 16:23:24 +0100 |
| commit | adb4907007445ab9d392f4ce398cd7fa5d26612b (patch) | |
| tree | 71fff7c808cd046a6b11e09d1861c428fea98624 /arch | |
| parent | c3b46c73264b03000d1e18b22f5caf63332547c9 (diff) | |
| download | linux-rpi3-adb4907007445ab9d392f4ce398cd7fa5d26612b.tar.gz linux-rpi3-adb4907007445ab9d392f4ce398cd7fa5d26612b.tar.bz2 linux-rpi3-adb4907007445ab9d392f4ce398cd7fa5d26612b.zip | |
arm64: fix invalidation of wrong __early_cpu_boot_status cacheline
In head.S, the str_l macro, which takes a source register, a symbol name
and a temp register, is used to store a status value to the variable
__early_cpu_boot_status. Subsequently, the value of the temp register is
reused to invalidate any cachelines covering this variable.
However, since str_l resolves to
adrp \tmp, \sym
str \src, [\tmp, :lo12:\sym]
the temp register never actually holds the address of the variable but
only of the 4 KB window that covers it, and reusing it leads to the
wrong cacheline being invalidated. So instead, take the address
explicitly before doing the store, and reuse that value to perform
the cache invalidation.
Fixes: bb9052744f4b ("arm64: Handle early CPU boot failures")
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Suzuki K Poulose <Suzuki.Poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/kernel/head.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 4203d5f257bc..80a709aa211a 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -734,7 +734,8 @@ ENDPROC(__secondary_switched) .macro update_early_cpu_boot_status status, tmp1, tmp2 mov \tmp2, #\status - str_l \tmp2, __early_cpu_boot_status, \tmp1 + adr_l \tmp1, __early_cpu_boot_status + str \tmp2, [\tmp1] dmb sy dc ivac, \tmp1 // Invalidate potentially stale cache line .endm |