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| author | Fabio Estevam <fabio.estevam@freescale.com> | 2013-09-05 16:02:57 -0300 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-09-17 10:04:24 +0800 |
| commit | 5d5248a6d110d9ec58c1c1525d338e28357a25c2 (patch) | |
| tree | fa680617a61643f3d90f5ec557a02f6accdb65b9 /arch/arm | |
| parent | bdb1b5f2ddd8a32fd0cd78bb68fc76c30266b27c (diff) | |
| download | linux-rpi3-5d5248a6d110d9ec58c1c1525d338e28357a25c2.tar.gz linux-rpi3-5d5248a6d110d9ec58c1c1525d338e28357a25c2.tar.bz2 linux-rpi3-5d5248a6d110d9ec58c1c1525d338e28357a25c2.zip | |
ARM: mach-imx: clk-imx51-imx53: Fix 'spdif1_pred' clock registration
Since commit beb2d1c1ba (ARM i.MX5: Add S/PDIF clocks), the following clock
error appears on mx51:
TrustZone Interrupt Controller (TZIC) initialized
i.MX51 clk 180: register failed with -17
i.MX5 clk 180: register failed with -17
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms
CPU identified as i.MX51, silicon rev 3.0
...
Clock 180 corresponds to 'spdif1_podf' and this clock is getting registered
twice.
Fix it, by properly registering the 'spdif1_pred' clock, which should not
reference 'spdif1_podf'.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx51-imx53.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 1a56a3319997..d9094b9a5185 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -397,7 +397,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel)); clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2, spdif_sel, ARRAY_SIZE(spdif_sel)); - clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3); + clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3); clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6); clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1, mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); |