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| author | Matthias Schiffer <matthias.schiffer@ew.tq-group.com> | 2024-05-08 15:37:44 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-07-11 12:49:09 +0200 |
| commit | b5f1844c05618b269097dc7d40f041e3f8784df0 (patch) | |
| tree | d2e4dfee101a64415abdbd0980e1bd9158599040 /drivers/tty | |
| parent | 586b41060113ae43032ec6c4a16d518cef5da6e0 (diff) | |
| download | linux-rpi-b5f1844c05618b269097dc7d40f041e3f8784df0.tar.gz linux-rpi-b5f1844c05618b269097dc7d40f041e3f8784df0.tar.bz2 linux-rpi-b5f1844c05618b269097dc7d40f041e3f8784df0.zip | |
serial: imx: Raise TX trigger level to 8
[ Upstream commit a3d8728ab079951741efa11360df43dbfacba7ab ]
At the default TX trigger level of 2 in non-DMA mode (meaning that an
interrupt is generated when less than 2 characters are left in the
FIFO), we have observed frequent buffer underruns at 115200 Baud on an
i.MX8M Nano. This can cause communication issues if the receiving side
expects a continuous transfer.
Increasing the level to 8 makes the UART trigger an interrupt earlier,
giving the kernel enough time to refill the FIFO, at the cost of
triggering one interrupt per ~24 instead of ~30 bytes of transmitted
data (as the i.MX UART has a 32 byte FIFO).
Signed-off-by: Michael Krummsdorf <michael.krummsdorf@tq-group.com>
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/20240508133744.35858-1-matthias.schiffer@ew.tq-group.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/tty')
| -rw-r--r-- | drivers/tty/serial/imx.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 285e0e1144c4..a5d0df2ba5c5 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -1320,7 +1320,7 @@ static void imx_uart_clear_rx_errors(struct imx_port *sport) } -#define TXTL_DEFAULT 2 /* reset default */ +#define TXTL_DEFAULT 8 #define RXTL_DEFAULT 8 /* 8 characters or aging timer */ #define TXTL_DMA 8 /* DMA burst setting */ #define RXTL_DMA 9 /* DMA burst setting */ |