summaryrefslogtreecommitdiff
path: root/arch/xtensa
diff options
context:
space:
mode:
authorMax Filippov <jcmvbkbc@gmail.com>2019-11-25 12:59:13 -0800
committerMax Filippov <jcmvbkbc@gmail.com>2022-05-01 19:51:23 -0700
commitdedfe2590bdf1beaaf064f1f1b71098b5fddbfe1 (patch)
treed689f083efe63f78745e6ca21cf54b53a9a27310 /arch/xtensa
parent0b549f813387231e0053c10dd7006e69ad4c5f95 (diff)
downloadlinux-rpi-dedfe2590bdf1beaaf064f1f1b71098b5fddbfe1.tar.gz
linux-rpi-dedfe2590bdf1beaaf064f1f1b71098b5fddbfe1.tar.bz2
linux-rpi-dedfe2590bdf1beaaf064f1f1b71098b5fddbfe1.zip
xtensa: add xtensa_xsr macro
xtensa_xsr does the XSR instruction for the specified special register. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa')
-rw-r--r--arch/xtensa/include/asm/processor.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h
index 4489a27d527a..76bc63127c66 100644
--- a/arch/xtensa/include/asm/processor.h
+++ b/arch/xtensa/include/asm/processor.h
@@ -246,6 +246,13 @@ extern unsigned long __get_wchan(struct task_struct *p);
v; \
})
+#define xtensa_xsr(x, sr) \
+ ({ \
+ unsigned int __v__ = (unsigned int)(x); \
+ __asm__ __volatile__ ("xsr %0, " __stringify(sr) : "+a"(__v__)); \
+ __v__; \
+ })
+
#if XCHAL_HAVE_EXTERN_REGS
static inline void set_er(unsigned long value, unsigned long addr)