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| author | Maciej W. Rozycki <macro@orcam.me.uk> | 2022-03-04 21:13:11 +0000 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2022-03-07 13:11:03 +0100 |
| commit | 6ddcba9d480b6bcced4223a729794dfa6becb7eb (patch) | |
| tree | 63af7340d6af11850fe73750dd003ec7714e8933 /arch/mips | |
| parent | 244eae91a94c6dab82b3232967d10eeb9dfa21c6 (diff) | |
| download | linux-rpi-6ddcba9d480b6bcced4223a729794dfa6becb7eb.tar.gz linux-rpi-6ddcba9d480b6bcced4223a729794dfa6becb7eb.tar.bz2 linux-rpi-6ddcba9d480b6bcced4223a729794dfa6becb7eb.zip | |
MIPS: Sanitise Cavium switch cases in TLB handler synthesizers
It makes no sense to fall through to `break'. Therefore reorder the
switch statements so as to have the Cavium cases first, followed by the
default case, which improves readability and pacifies code analysis
tools. No change in semantics, assembly produced is exactly the same.
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Fixes: bc431d2153cc ("MIPS: Fix fall-through warnings for Clang")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/mm/tlbex.c | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index d9df2c43b15c..8dbbd99fc7e8 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2159,16 +2159,14 @@ static void build_r4000_tlb_load_handler(void) uasm_i_tlbr(&p); switch (current_cpu_type()) { - default: - if (cpu_has_mips_r2_exec_hazard) { - uasm_i_ehb(&p); - fallthrough; - case CPU_CAVIUM_OCTEON: case CPU_CAVIUM_OCTEON_PLUS: case CPU_CAVIUM_OCTEON2: - break; - } + break; + default: + if (cpu_has_mips_r2_exec_hazard) + uasm_i_ehb(&p); + break; } /* Examine entrylo 0 or 1 based on ptr. */ @@ -2235,15 +2233,14 @@ static void build_r4000_tlb_load_handler(void) uasm_i_tlbr(&p); switch (current_cpu_type()) { - default: - if (cpu_has_mips_r2_exec_hazard) { - uasm_i_ehb(&p); - case CPU_CAVIUM_OCTEON: case CPU_CAVIUM_OCTEON_PLUS: case CPU_CAVIUM_OCTEON2: - break; - } + break; + default: + if (cpu_has_mips_r2_exec_hazard) + uasm_i_ehb(&p); + break; } /* Examine entrylo 0 or 1 based on ptr. */ |