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authorStephen Boyd <sboyd@kernel.org>2020-08-03 15:06:53 -0700
committerStephen Boyd <sboyd@kernel.org>2020-08-03 15:06:53 -0700
commit53e07424eca922fb7a15f34ad9767b73fced8a05 (patch)
tree71aff46caddf8fee64c49785e0ac681f86ac4dea /MAINTAINERS
parent987106e5f2f03fc0b6450804dc8423bea2bbc47c (diff)
parentcb7c6677bfb5c92526df73b20760d65bd9189344 (diff)
parentaab58ace0d14558af73dbc4c4b066000a60deab0 (diff)
parent9f7d5042a64160e20c73d734f9ed5dd8c6bba205 (diff)
parentd310124cd99df5e5011d79f36a6d16d3452de348 (diff)
parent03111b1088f18f93d38e888c41e8a1e6aba9f8bb (diff)
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Merge branches 'clk-actions', 'clk-rockchip', 'clk-iproc', 'clk-intel' and 'clk-debugfs' into clk-next
- RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs * clk-actions: MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs clk: actions: Add Actions S500 SoC Reset Management Unit support dt-bindings: reset: Add binding constants for Actions S500 RMU clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC clk: actions: Fix h_clk for Actions S500 SoC * clk-rockchip: clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328" clk: rockchip: use separate compatibles for rk3288w-cru dt-bindings: clocks: add rk3288w variant compatible clk: rockchip: Handle clock tree for rk3288w variant clk: rockchip: convert rk3036 pll type to use internal lock status clk: rockchip: convert basic pll lock_wait to use regmap_read_poll_timeout clk: rockchip: convert rk3399 pll type to use readl_relaxed_poll_timeout * clk-iproc: clk: iproc: round clock rate to the closest * clk-intel: clk: intel: Avoid unnecessary memset by improving code clk: intel: Improve locking in the driver clk: intel: Use devm_clk_hw_register() instead of clk_hw_register() * clk-debugfs: clk: Add support for enabling/disabling clocks from debugfs