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| author | Jim Quinlan <jim2101024@gmail.com> | 2022-01-06 11:03:25 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2022-01-12 13:45:50 -0600 |
| commit | 504253e44a9dc91e535f84273ebded324de4d2f6 (patch) | |
| tree | efa626e0403852b89a4736b56bed6b60c74b1fad /Documentation/devicetree | |
| parent | 41ac424ac188d9d04c9831fd0fe6bce73ae2ec03 (diff) | |
| download | linux-rpi-504253e44a9dc91e535f84273ebded324de4d2f6.tar.gz linux-rpi-504253e44a9dc91e535f84273ebded324de4d2f6.tar.bz2 linux-rpi-504253e44a9dc91e535f84273ebded324de4d2f6.zip | |
dt-bindings: PCI: Correct brcmstb interrupts, interrupt-map.
The "pcie" and "msi" interrupts were given the same interrupt when they are
actually different. Interrupt-map only had the INTA entry; add the INTB,
INTC, and INTD entries.
Link: https://lore.kernel.org/r/20220106160332.2143-3-jim2101024@gmail.com
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 1fe102743f82..22f2ef446f18 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -143,11 +143,15 @@ examples: #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; - interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pcie", "msi"; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + msi-parent = <&pcie0>; msi-controller; ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>; |