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| author | Anson Huang <Anson.Huang@nxp.com> | 2020-02-26 17:13:49 +0800 |
|---|---|---|
| committer | Philipp Zabel <p.zabel@pengutronix.de> | 2020-05-06 12:03:43 +0200 |
| commit | c4e181d6fec49033f8f2c1b2d8b1de538ad4cd11 (patch) | |
| tree | c3ca5a4188b5a4eb6bd3355dc84cf79692d48c24 /include/dt-bindings/reset | |
| parent | ecd910f4420aa805f6f17050f0d9f31910189bee (diff) | |
| download | linux-riscv-c4e181d6fec49033f8f2c1b2d8b1de538ad4cd11.tar.gz linux-riscv-c4e181d6fec49033f8f2c1b2d8b1de538ad4cd11.tar.bz2 linux-riscv-c4e181d6fec49033f8f2c1b2d8b1de538ad4cd11.zip | |
dt-bindings: reset: imx7: Document usage on i.MX8MP SoC
The driver now supports i.MX8MP, so update bindings accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'include/dt-bindings/reset')
| -rw-r--r-- | include/dt-bindings/reset/imx8mp-reset.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h new file mode 100644 index 000000000000..2e8c9104b666 --- /dev/null +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 NXP + */ + +#ifndef DT_BINDING_RESET_IMX8MP_H +#define DT_BINDING_RESET_IMX8MP_H + +#define IMX8MP_RESET_A53_CORE_POR_RESET0 0 +#define IMX8MP_RESET_A53_CORE_POR_RESET1 1 +#define IMX8MP_RESET_A53_CORE_POR_RESET2 2 +#define IMX8MP_RESET_A53_CORE_POR_RESET3 3 +#define IMX8MP_RESET_A53_CORE_RESET0 4 +#define IMX8MP_RESET_A53_CORE_RESET1 5 +#define IMX8MP_RESET_A53_CORE_RESET2 6 +#define IMX8MP_RESET_A53_CORE_RESET3 7 +#define IMX8MP_RESET_A53_DBG_RESET0 8 +#define IMX8MP_RESET_A53_DBG_RESET1 9 +#define IMX8MP_RESET_A53_DBG_RESET2 10 +#define IMX8MP_RESET_A53_DBG_RESET3 11 +#define IMX8MP_RESET_A53_ETM_RESET0 12 +#define IMX8MP_RESET_A53_ETM_RESET1 13 +#define IMX8MP_RESET_A53_ETM_RESET2 14 +#define IMX8MP_RESET_A53_ETM_RESET3 15 +#define IMX8MP_RESET_A53_SOC_DBG_RESET 16 +#define IMX8MP_RESET_A53_L2RESET 17 +#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18 +#define IMX8MP_RESET_OTG1_PHY_RESET 19 +#define IMX8MP_RESET_OTG2_PHY_RESET 20 +#define IMX8MP_RESET_SUPERMIX_RESET 21 +#define IMX8MP_RESET_AUDIOMIX_RESET 22 +#define IMX8MP_RESET_MLMIX_RESET 23 +#define IMX8MP_RESET_PCIEPHY 24 +#define IMX8MP_RESET_PCIEPHY_PERST 25 +#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26 +#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27 +#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28 +#define IMX8MP_RESET_MEDIA_RESET 29 +#define IMX8MP_RESET_GPU2D_RESET 30 +#define IMX8MP_RESET_GPU3D_RESET 31 +#define IMX8MP_RESET_GPU_RESET 32 +#define IMX8MP_RESET_VPU_RESET 33 +#define IMX8MP_RESET_VPU_G1_RESET 34 +#define IMX8MP_RESET_VPU_G2_RESET 35 +#define IMX8MP_RESET_VPUVC8KE_RESET 36 +#define IMX8MP_RESET_NOC_RESET 37 + +#define IMX8MP_RESET_NUM 38 + +#endif |