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| author | Johan Hovold <johan@kernel.org> | 2014-11-19 12:59:20 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-11-21 14:08:57 -0500 |
| commit | 6d01329444725a5c17cf75ba6c5c0c5e42843613 (patch) | |
| tree | 1e4025ecba1b33a5419a95717f74c259a6add275 /Documentation | |
| parent | 86dc1342bcbb1905b2ac9653a559b303f62bd728 (diff) | |
| download | linux-exynos-6d01329444725a5c17cf75ba6c5c0c5e42843613.tar.gz linux-exynos-6d01329444725a5c17cf75ba6c5c0c5e42843613.tar.bz2 linux-exynos-6d01329444725a5c17cf75ba6c5c0c5e42843613.zip | |
dt/bindings: reformat micrel eth-phy documentation
Reduce indentation of Micrel PHY binding documentations somewhat.
Also fix "reference input clock" typo while at it.
Cc: devicetree@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/net/micrel.txt | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/Documentation/devicetree/bindings/net/micrel.txt b/Documentation/devicetree/bindings/net/micrel.txt index a1bab5eaae02..20a6cac7abc6 100644 --- a/Documentation/devicetree/bindings/net/micrel.txt +++ b/Documentation/devicetree/bindings/net/micrel.txt @@ -6,21 +6,21 @@ Optional properties: - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs. - Configure the LED mode with single value. The list of PHYs and - the bits that are currently supported: + Configure the LED mode with single value. The list of PHYs and the + bits that are currently supported: - KSZ8001: register 0x1e, bits 15..14 - KSZ8041: register 0x1e, bits 15..14 - KSZ8021: register 0x1f, bits 5..4 - KSZ8031: register 0x1f, bits 5..4 - KSZ8051: register 0x1f, bits 5..4 - KSZ8081: register 0x1f, bits 5..4 - KSZ8091: register 0x1f, bits 5..4 + KSZ8001: register 0x1e, bits 15..14 + KSZ8041: register 0x1e, bits 15..14 + KSZ8021: register 0x1f, bits 5..4 + KSZ8031: register 0x1f, bits 5..4 + KSZ8051: register 0x1f, bits 5..4 + KSZ8081: register 0x1f, bits 5..4 + KSZ8091: register 0x1f, bits 5..4 - See the respective PHY datasheet for the mode values. + See the respective PHY datasheet for the mode values. - clocks, clock-names: contains clocks according to the common clock bindings. - supported clocks: - - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII - refence input clock. Used to determine the XI input clock. + supported clocks: + - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference + input clock. Used to determine the XI input clock. |