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| author | Lucas Stach <dev@lynxeye.de> | 2015-05-09 22:06:54 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2015-05-13 10:46:07 +0200 |
| commit | 9cf82e72ec449b4516843377ac7a20abe300c64f (patch) | |
| tree | a4092cab1149aec4c38bea7e4a21927265862a36 | |
| parent | 030bbdbf4c833bc69f502eae58498bc5572db736 (diff) | |
| download | linux-exynos-9cf82e72ec449b4516843377ac7a20abe300c64f.tar.gz linux-exynos-9cf82e72ec449b4516843377ac7a20abe300c64f.tar.bz2 linux-exynos-9cf82e72ec449b4516843377ac7a20abe300c64f.zip | |
irqchip: tegra: Set the proper base address in irq chip data
The irq chip functions use the irq chipdata directly as the base register
address of the controller, so this should be passed in instead of a pointer
to the array address holding the base address.
This fixes Tegra20 CPUidle as now the un-/masking of IRQs at the LIC level
works again, but more importantly it fixes the resulting memory corruption.
Fixes: de3ce0804916 ' irqchip: tegra: Add DT-based support for legacy interrupt controller'
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Link: http://lkml.kernel.org/r/1431202014-3136-1-git-send-email-dev@lynxeye.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| -rw-r--r-- | drivers/irqchip/irq-tegra.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c index 51c485d9a877..f67bbd80433e 100644 --- a/drivers/irqchip/irq-tegra.c +++ b/drivers/irqchip/irq-tegra.c @@ -264,7 +264,7 @@ static int tegra_ictlr_domain_alloc(struct irq_domain *domain, irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, &tegra_ictlr_chip, - &info->base[ictlr]); + info->base[ictlr]); } parent_args = *args; |