summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2014-02-13drm/i915: VLV2 - Fix hotplug detect bitsTodd Previte1-3/+7
2013-10-05drm/i915: fix gen4 digital port hotplug definitionsDaniel Vetter1-3/+9
2013-09-07drm/i915: ivb: fix edp voltage swing reg valImre Deak1-1/+1
2013-08-29drm/i915: Invalidate TLBs for the rings after a resetChris Wilson1-0/+2
2013-07-25drm/i915: Fix context sizes on HSWBen Widawsky1-8/+7
2013-07-25drm/i915: Fix up sdvo hpd pins for i965g/gmDaniel Vetter1-7/+6
2013-05-07Revert "drm/i915: Calculate correct stolen size for GEN7+"Ben Widawsky1-2/+0
2013-04-23drm/i915: Make data/link N value power of twoVille Syrjälä1-8/+4
2013-04-18drm/i915: preserve the PBC bits of TRANS_CHICKEN2Paulo Zanoni1-2/+5
2013-04-18drm/i915: set CPT FDI RX polarity bits based on VBTPaulo Zanoni1-1/+1
2013-04-18drm/i915: Scale ring, rather than ia, frequency on HaswellChris Wilson1-0/+4
2013-04-18drm/i915: Increase max fence pitch limit to 256KB on IVB+Ville Syrjälä1-0/+1
2013-04-18drm/i915: Configure GAM_ECOCHK appropriatly for Gen7Ville Syrjälä1-0/+5
2013-04-18drm/i915: Add ECOBITS_SNB_BITVille Syrjälä1-0/+1
2013-04-08drm/i915: Don't wait for PCH on resetBen Widawsky1-0/+3
2013-04-02drm/i915: add Punit read/write routines for VLV v2Jesse Barnes1-0/+14
2013-04-02drm/i915: panel power sequencing for VLV eDP v2Jesse Barnes1-0/+9
2013-04-02drm/i915: sprite support for ValleyView v4Jesse Barnes1-0/+57
2013-04-02drm/i915: fix ILK GPU reset for renderJesse Barnes1-0/+1
2013-03-27drm/i915: wire up SDVO hpd support on cpt/pptDaniel Vetter1-0/+2
2013-03-26DRM/i915: Convert HPD interrupts to make use of HPD pin assignment in encoder...Egbert Eich1-1/+31
2013-03-26drm/i915: HSW PM Frequency bits fixRodrigo Vivi1-0/+1
2013-03-23drm/i915: Implement WaSwitchSolVfFArbitrationPriorityBen Widawsky1-0/+1
2013-03-23drm/i915: DSPFW and BLC regs are in the display offset rangeJesse Barnes1-3/+5
2013-03-23drm/i915: add media well to VLV force wake routines v2Jesse Barnes1-0/+2
2013-03-19Merge tag 'v3.9-rc3' into drm-intel-next-queuedDaniel Vetter1-2/+2
2013-03-19drm/i915: allow force wake at init time on VLV v2Jesse Barnes1-0/+2
2013-03-06drm/i915: Fix incorrect definition of ADPA HSYNC and VSYNC bitsPatrik Jakobsson1-2/+2
2013-03-04drm/i915: rename some HDMI bit definitionsPaulo Zanoni1-3/+3
2013-03-04drm/i915: remove duplicated SDVO/HDMI bit definitionsPaulo Zanoni1-11/+6
2013-03-04drm/i915: unify the definitions of the HDMI/SDVO registerPaulo Zanoni1-56/+55
2013-03-04drm/i915: clarify confusion between SDVO and HDMI registersPaulo Zanoni1-10/+9
2013-03-03drm/i915: Use cpu_transcoder for HSW_TVIDEO_DIP_* instead of pipeRodrigo Vivi1-8/+10
2013-02-20drm/i915: Refactor gen2 to gen4 vblank interrupt handlingVille Syrjälä1-0/+1
2013-02-20drm/i915: use FPGA_DBG for the "unclaimed register" checksPaulo Zanoni1-0/+3
2013-02-20drm/i915: Implement pipe CSC based limited range RGB outputVille Syrjälä1-1/+51
2013-02-20drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+Ville Syrjälä1-0/+1
2013-02-20drm/i915: Preserve the DDI link reversal configurationDamien Lespiau1-0/+1
2013-02-20drm/i915: Preserve the FDI line reversal override bit on CPTDamien Lespiau1-1/+1
2013-02-20drm/i915: detect wrong MCH watermark valuesDaniel Vetter1-0/+4
2013-02-15drm/i915: unify HDMI/DP hpd definitionsDaniel Vetter1-19/+9
2013-02-14drm/i915: Fix RC6VIDS encode/decodeBen Widawsky1-2/+2
2013-02-08Merge branch 'fbcon-locking-fixes' of ssh://people.freedesktop.org/~airlied/l...Dave Airlie1-0/+3
2013-01-31drm/i915: Introduce i915_vgacntrl_reg()Ville Syrjälä1-0/+2
2013-01-31drm/i915: Fix CAGF for HSWBen Widawsky1-0/+2
2013-01-28drm/i915: Implement WaVSRefCountFullforceMissDisableBen Widawsky1-0/+1
2013-01-26drm/i915: fix intel_init_power_wellsPaulo Zanoni1-4/+4
2013-01-26drm/i915: SWF screatch registers need an offset on VLVVille Syrjälä1-13/+13
2013-01-26drm/i915: Include display_mmio_offset in sequencer index/data registersVille Syrjälä1-2/+8
2013-01-26drm/i915: PLL registers need an offset on VLVVille Syrjälä1-4/+4
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-01 19:20:02 +0000