summaryrefslogtreecommitdiff
path: root/arch/mips/mm/c-r4k.c
AgeCommit message (Expand)AuthorFilesLines
2006-07-13[MIPS] vr41xx: Replace magic number for P4K bit with symbol.Yoichi Yuasa1-1/+1
2006-07-13[MIPS] vr41xx: Changed workaround to recommended methodYoichi Yuasa1-4/+3
2006-07-13[MIPS] VR41xx: Set VR41_CONF_BP only for PrId 0x0c80.Yoichi Yuasa1-1/+3
2006-07-13[MIPS] Use the proper technical term for naming some of the cache macros.Ralf Baechle1-4/+4
2006-06-30Remove obsolete #include <linux/config.h>Jörn Engel1-1/+0
2006-06-29[MIPS] 74K: Assume it will also have an AR bit in config7Ralf Baechle1-0/+1
2006-06-29[MIPS] Treat CPUs with AR bit as physically indexed.Ralf Baechle1-3/+8
2006-06-29[MIPS] Fix handling of 0 length I & D caches.Chris Dearman1-23/+41
2006-06-29[MIPS] MIPS32/MIPS64 secondary cache managementChris Dearman1-5/+18
2006-06-06[MIPS] Save write-only Config.OD from being clobberedSergei Shtylyov1-0/+34
2006-06-01[MIPS] Treat R14000 like R10000.Kumba1-0/+4
2006-06-01[MIPS] Fix deadlock on MP with cache aliases.Ralf Baechle1-9/+30
2006-06-01[MIPS] Add missing 34K processor IDsNigel Stephens1-0/+1
2006-04-19[MIPS] Use __ffs() instead of ffs() for waybit calculation.Atsushi Nemoto1-8/+8
2006-04-19[MIPS] Handle IDE PIO cache aliases on SMP.Ralf Baechle1-0/+1
2006-04-19[MIPS] Fix tx49_blast_icache32_page_indexed.Atsushi Nemoto1-1/+2
2006-03-21[MIPS] TX49XX has prefetch.Atsushi Nemoto1-0/+1
2006-03-18[MIPS] local_r4k_flush_cache_page fixAtsushi Nemoto1-4/+9
2006-02-28[MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.Ralf Baechle1-5/+11
2006-02-14[MIPS] Add protected_blast_icache_range, blast_icache_range, etc.Atsushi Nemoto1-90/+14
2006-02-07[MIPS] Remove wrong __user tags.Atsushi Nemoto1-4/+3
2006-01-10MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle1-2/+2
2005-10-29Rename page argument of flush_cache_page to something more descriptive.Ralf Baechle1-16/+17
2005-10-29Cleanup the mess in cpu_cache_init.Ralf Baechle1-1/+1
2005-10-29Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer1-0/+1
2005-10-29Minor code cleanup.Thiemo Seufer1-15/+15
2005-10-29More .set push/pop.Thiemo Seufer1-2/+2
2005-10-29Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer1-2/+2
2005-10-29Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle1-3/+2
2005-10-29More AP / SP bits for the 34K, the Malta bits and things. Still wantsRalf Baechle1-2/+1
2005-10-29Mark a few variables __read_mostly.Ralf Baechle1-1/+7
2005-10-29MIPS R2 instruction hazard handling.Ralf Baechle1-0/+1
2005-10-29Better interface to run uncached cache setup code.Thiemo Seufer1-4/+2
2005-10-29Sparseify MIPS.Ralf Baechle1-3/+4
2005-10-29Base Au1200 2.6 support.Pete Popov1-0/+4
2005-10-29Use intermediate variable.Thiemo Seufer1-3/+3
2005-10-29Moves a test which determines if we actually need to perform aRalf Baechle1-7/+7
2005-10-29Update MIPS to use the 4-level pagetable code thereby getting rid ofRalf Baechle1-1/+3
2005-10-2925Kf is also physically indexed.Ralf Baechle1-0/+1
2005-10-2920Kc and SB1 don't suffer from aliases.Ralf Baechle1-0/+2
2005-10-29Move missplaced code line to the right place.Ralf Baechle1-3/+2
2005-10-29Use hardware mechanism to deal with cache aliases in the 24K.Ralf Baechle1-2/+10
2005-10-29Remove old wrong bits of cache code.Ralf Baechle1-3/+0
2005-09-05[PATCH] mips: nuke trailing whitespaceRalf Baechle1-8/+8
2005-09-05[PATCH] mips: clean up 32/64-bit configurationRalf Baechle1-2/+2
2005-04-16Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds1-0/+1260
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 10:21:46 +0000