index
:
platform/kernel/linux-3.10
accepted/tizen_3.0.2014.q3_common
accepted/tizen_3.0.2015.q2_common
accepted/tizen_common
accepted/tizen_ivi
accepted/tizen_mobile
accepted/tizen_tv
accepted/tizen_wearable
devel/aarch64
devel/tizen
devel/v3.10-ltsi
dmafence
kdbus-integration
master
sandbox/cometzero/tizen
sandbox/cosmichobo/tizen
sandbox/daeinki/tizen
sandbox/hwhwang7/tizen
sandbox/mchehab/tizen-media-backports
sandbox/mwereski/kdbus-integration
sandbox/pawelo/kdbus-next-wip
sandbox/pawelo/kdbus-next-wip-next
sandbox/pawelo/kdbus-v4-backport
sandbox/pawelo/kernfs
sandbox/pawelo/kernfs_better
sandbox/pawelo/sysfs
sandbox/pcoval/tizen
tizen
tizen-rebase-20140515
tizen_3.0.2014.q3_common
tizen_3.0.2014.q4_common
tizen_3.0.2015.q1_common
tizen_3.0.2015.q2_common
tizen_3.0.m1_mobile
tizen_3.0.m1_tv
tizen_LPD
upstream
v3.10.51-integration
v3.10.52-integration
v3.10.60-rebase
Domain: System / Kernel;
Inki Dae <inki.dae@samsung.com>
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path:
root
/
arch
/
arm
/
mm
/
proc-v7-2level.S
Age
Commit message (
Expand
)
Author
Files
Lines
2014-05-06
ARM: 7954/1: mm: remove remaining domain support from ARMv6
Will Deacon
1
-7
/
+0
2013-08-11
ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2
Will Deacon
1
-1
/
+1
2013-04-03
ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead
Will Deacon
1
-1
/
+2
2013-02-16
ARM: 7650/1: mm: replace direct access to mm->context.id with new macro
Ben Dooks
1
-1
/
+1
2012-11-09
ARM: mm: introduce present, faulting entries for PAGE_NONE
Will Deacon
1
-0
/
+4
2012-11-09
ARM: mm: introduce L_PTE_VALID for page table entries
Will Deacon
1
-1
/
+1
2012-11-09
ARM: mm: don't use the access flag permissions mechanism for classic MMU
Will Deacon
1
-2
/
+2
2012-07-09
ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current process
Will Deacon
1
-0
/
+5
2012-04-17
ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs
Catalin Marinas
1
-3
/
+0
2012-04-17
ARM: Use TTBR1 instead of reserved context ID
Will Deacon
1
-6
/
+4
2011-12-08
ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.S
Catalin Marinas
1
-0
/
+171