diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pci/pci.c | 6 | ||||
| -rw-r--r-- | drivers/pci/pcie/aer/aerdrv.c | 10 | ||||
| -rw-r--r-- | drivers/pci/probe.c | 23 |
3 files changed, 16 insertions, 23 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 5ea587e59e4..37499127c80 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -679,7 +679,7 @@ static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) */ int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) { - return state > PCI_D0 ? + return state >= PCI_D0 ? pci_platform_power_transition(dev, state) : -EINVAL; } EXPORT_SYMBOL_GPL(__pci_complete_power_transition); @@ -716,10 +716,6 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state) */ return 0; - /* Check if we're already there */ - if (dev->current_state == state) - return 0; - __pci_start_power_transition(dev, state); /* This device is quirked not to be put into D3, so diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c index aa495ad9bbd..7a711ee314b 100644 --- a/drivers/pci/pcie/aer/aerdrv.c +++ b/drivers/pci/pcie/aer/aerdrv.c @@ -244,11 +244,17 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) /* Assert Secondary Bus Reset */ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &p2p_ctrl); - p2p_ctrl |= PCI_CB_BRIDGE_CTL_CB_RESET; + p2p_ctrl |= PCI_BRIDGE_CTL_BUS_RESET; pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl); + /* + * we should send hot reset message for 2ms to allow it time to + * propogate to all downstream ports + */ + msleep(2); + /* De-assert Secondary Bus Reset */ - p2p_ctrl &= ~PCI_CB_BRIDGE_CTL_CB_RESET; + p2p_ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl); /* diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 882bd8d29fe..c82548afcd5 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -174,19 +174,14 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, pci_read_config_dword(dev, pos, &sz); pci_write_config_dword(dev, pos, l); - if (!sz) - goto fail; /* BAR not implemented */ - /* * All bits set in sz means the device isn't working properly. - * If it's a memory BAR or a ROM, bit 0 must be clear; if it's - * an io BAR, bit 1 must be clear. + * If the BAR isn't implemented, all bits must be 0. If it's a + * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit + * 1 must be clear. */ - if (sz == 0xffffffff) { - dev_err(&dev->dev, "reg %x: invalid size %#x; broken device?\n", - pos, sz); + if (!sz || sz == 0xffffffff) goto fail; - } /* * I don't know how l can have all bits set. Copied from old code. @@ -249,17 +244,13 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, pos, res); } } else { - u32 size = pci_size(l, sz, mask); + sz = pci_size(l, sz, mask); - if (!size) { - dev_err(&dev->dev, "reg %x: invalid size " - "(l %#x sz %#x mask %#x); broken device?", - pos, l, sz, mask); + if (!sz) goto fail; - } res->start = l; - res->end = l + size; + res->end = l + sz; dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res); } |