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-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index c44ca1ee1b8..4478757b930 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -292,7 +292,7 @@ static struct clksrc_sources exynos5_clk_src_mpll = {
.nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
};
-struct clksrc_clk exynos5_clk_mout_mpll = {
+static struct clksrc_clk exynos5_clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
},
@@ -467,12 +467,12 @@ static struct clksrc_clk exynos5_clk_pclk_acp = {
/* Core list of CMU_TOP side */
-struct clk *exynos5_clkset_aclk_top_list[] = {
+static struct clk *exynos5_clkset_aclk_top_list[] = {
[0] = &exynos5_clk_mout_mpll_user.clk,
[1] = &exynos5_clk_mout_bpll_user.clk,
};
-struct clksrc_sources exynos5_clkset_aclk = {
+static struct clksrc_sources exynos5_clkset_aclk = {
.sources = exynos5_clkset_aclk_top_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
};
@@ -486,12 +486,12 @@ static struct clksrc_clk exynos5_clk_aclk_400 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
};
-struct clk *exynos5_clkset_aclk_333_166_list[] = {
+static struct clk *exynos5_clkset_aclk_333_166_list[] = {
[0] = &exynos5_clk_mout_cpll.clk,
[1] = &exynos5_clk_mout_mpll_user.clk,
};
-struct clksrc_sources exynos5_clkset_aclk_333_166 = {
+static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
.sources = exynos5_clkset_aclk_333_166_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
};
@@ -966,7 +966,7 @@ static struct clk exynos5_clk_fimd1 = {
.ctrlbit = (1 << 0),
};
-struct clk *exynos5_clkset_group_list[] = {
+static struct clk *exynos5_clkset_group_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = NULL,
[2] = &exynos5_clk_sclk_hdmi24m,
@@ -979,7 +979,7 @@ struct clk *exynos5_clkset_group_list[] = {
[9] = &exynos5_clk_mout_cpll.clk,
};
-struct clksrc_sources exynos5_clkset_group = {
+static struct clksrc_sources exynos5_clkset_group = {
.sources = exynos5_clkset_group_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
};
@@ -1195,7 +1195,7 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
};
-struct clksrc_clk exynos5_clk_sclk_fimd1 = {
+static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
.clk = {
.name = "sclk_fimd",
.devname = "exynos5-fb.1",
@@ -1476,7 +1476,7 @@ static void exynos5_clock_resume(void)
#define exynos5_clock_resume NULL
#endif
-struct syscore_ops exynos5_clock_syscore_ops = {
+static struct syscore_ops exynos5_clock_syscore_ops = {
.suspend = exynos5_clock_suspend,
.resume = exynos5_clock_resume,
};