diff options
| -rw-r--r-- | arch/powerpc/boot/dts/mpc8540ads.dts | 16 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/mpc8548cds.dts | 16 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/mpc8560ads.dts | 18 |
3 files changed, 49 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts index f261d647ac8..d91e81c009f 100644 --- a/arch/powerpc/boot/dts/mpc8540ads.dts +++ b/arch/powerpc/boot/dts/mpc8540ads.dts @@ -48,6 +48,22 @@ reg = <e0000000 00100000>; // CCSRBAR 1M bus-frequency = <0>; + memory-controller@2000 { + compatible = "fsl,8540-memory-controller"; + reg = <2000 1000>; + interrupt-parent = <&mpic>; + interrupts = <2 2>; + }; + + l2-cache-controller@20000 { + compatible = "fsl,8540-l2-cache-controller"; + reg = <20000 1000>; + cache-line-size = <20>; // 32 bytes + cache-size = <40000>; // L2, 256K + interrupt-parent = <&mpic>; + interrupts = <0 2>; + }; + i2c@3000 { device_type = "i2c"; compatible = "fsl-i2c"; diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index b2b2200d042..ad96381033c 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -48,6 +48,22 @@ reg = <e0000000 00100000>; // CCSRBAR 1M bus-frequency = <0>; + memory-controller@2000 { + compatible = "fsl,8548-memory-controller"; + reg = <2000 1000>; + interrupt-parent = <&mpic>; + interrupts = <2 2>; + }; + + l2-cache-controller@20000 { + compatible = "fsl,8548-l2-cache-controller"; + reg = <20000 1000>; + cache-line-size = <20>; // 32 bytes + cache-size = <80000>; // L2, 512K + interrupt-parent = <&mpic>; + interrupts = <0 2>; + }; + i2c@3000 { device_type = "i2c"; compatible = "fsl-i2c"; diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts index 1f2afe9291d..80682152b0c 100644 --- a/arch/powerpc/boot/dts/mpc8560ads.dts +++ b/arch/powerpc/boot/dts/mpc8560ads.dts @@ -48,6 +48,22 @@ reg = <e0000000 00000200>; bus-frequency = <13ab6680>; + memory-controller@2000 { + compatible = "fsl,8540-memory-controller"; + reg = <2000 1000>; + interrupt-parent = <&mpic>; + interrupts = <2 2>; + }; + + l2-cache-controller@20000 { + compatible = "fsl,8540-l2-cache-controller"; + reg = <20000 1000>; + cache-line-size = <20>; // 32 bytes + cache-size = <40000>; // L2, 256K + interrupt-parent = <&mpic>; + interrupts = <0 2>; + }; + mdio@24520 { device_type = "mdio"; compatible = "gianfar"; @@ -110,7 +126,7 @@ #address-cells = <3>; compatible = "85xx"; device_type = "pci"; - reg = <8000 400>; + reg = <8000 1000>; clock-frequency = <3f940aa>; interrupt-map-mask = <f800 0 0 7>; interrupt-map = < |