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| author | Will Deacon <will.deacon@arm.com> | 2011-10-03 18:30:53 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-10-15 11:04:22 +0100 |
| commit | 29a541f6c1f6e4a85628bb86071b9e72c9f8be2c (patch) | |
| tree | 9f132fd63c08266901f3427d624891ac7e2da7b7 /virt | |
| parent | 002ea9eefec98dada56fd5f8e432a4e8570c2a26 (diff) | |
| download | linux-3.10-29a541f6c1f6e4a85628bb86071b9e72c9f8be2c.tar.gz linux-3.10-29a541f6c1f6e4a85628bb86071b9e72c9f8be2c.tar.bz2 linux-3.10-29a541f6c1f6e4a85628bb86071b9e72c9f8be2c.zip | |
ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9
Using COHERENT_LINE_{MISS,HIT} for cache misses and references
respectively is completely wrong. Instead, use the L1D events which
are a better and more useful approximation despite ignoring instruction
traffic.
Reported-by: Alasdair Grant <alasdair.grant@arm.com>
Reported-by: Matt Horsnell <matt.horsnell@arm.com>
Reported-by: Michael Williams <michael.williams@arm.com>
Cc: stable@kernel.org
Cc: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'virt')
0 files changed, 0 insertions, 0 deletions