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| author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-04-02 11:41:55 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-04-02 11:41:55 -0700 |
| commit | 9a5ee4cc9ef8de5185114237a81f5f395e21d8fd (patch) | |
| tree | 378d367ba1d97304051d3be0cec901fe8ab38d60 /include | |
| parent | b6a8b316c667f914c198a2de62e6729f359b7931 (diff) | |
| parent | a369a7100da3b4f5c2269be25160653d2c7013fc (diff) | |
| download | linux-3.10-9a5ee4cc9ef8de5185114237a81f5f395e21d8fd.tar.gz linux-3.10-9a5ee4cc9ef8de5185114237a81f5f395e21d8fd.tar.bz2 linux-3.10-9a5ee4cc9ef8de5185114237a81f5f395e21d8fd.zip | |
Merge branch 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6
* 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6:
[PATCH] x86: Don't probe for DDC on VBE1.2
[PATCH] x86-64: Increase NMI watchdog probing timeout
[PATCH] x86-64: Let oprofile reserve MSR on all CPUs
[PATCH] x86-64: Disable local APIC timer use on AMD systems with C1E
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-i386/cpufeature.h | 1 | ||||
| -rw-r--r-- | include/asm-i386/msr.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h index 3f92b94e0d7..d1b8e4ab6c1 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-i386/cpufeature.h @@ -75,6 +75,7 @@ #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ +#define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h index ec3b6803fd3..2ad3f30b1a6 100644 --- a/include/asm-i386/msr.h +++ b/include/asm-i386/msr.h @@ -275,6 +275,8 @@ static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) #define MSR_K7_FID_VID_CTL 0xC0010041 #define MSR_K7_FID_VID_STATUS 0xC0010042 +#define MSR_K8_ENABLE_C1E 0xC0010055 + /* extended feature register */ #define MSR_EFER 0xc0000080 |