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authorOr Gerlitz <ogerlitz@mellanox.com>2011-12-11 16:40:05 +0200
committerRoland Dreier <roland@purestorage.com>2012-01-03 21:00:02 -0800
commit9106c410697427363517ca6b4f463698aebc5f25 (patch)
treeddf079aeac48c40b479bb782f7e3de49153fca03 /fs/aio.c
parent5f0a6e2d503896062f641639dacfe5055c2f593b (diff)
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IB/mlx4: Fix SL to 802.1Q priority-bits mapping for IBoE
For IBoE, SLs 0-7 are mapped to Ethernet 802.1Q user priority bits (pbits) which are part of the VLAN tag, SLs 8-15 are reserved. Under Ethernet, the ConnectX firmware treats (decode/encode) the four bit SL field in various constructs such as QPC / UD WQE / CQE as PPP0 and not as 0PPP. This correlates well to the fact that within the vlan tag the pbits are located in bits 15-13 and not 12-14. The current code wasn't consistent around that area - the encoding was correct for the IBoE QPC.path.schedule_queue field, but was wrong for IBoE CQEs and when MLX header was built. These inconsistencies resulted in wrong SL <--> wire 802.1Q pbits mapping, which is fixed by using SL <--> PPP0 all around the place. Signed-off-by: Oren Duer <oren@mellanox.co.il> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
Diffstat (limited to 'fs/aio.c')
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