diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2011-02-07 13:08:16 +1000 |
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committer | Ben Skeggs <bskeggs@redhat.com> | 2011-02-25 06:45:05 +1000 |
commit | 292deb7a3b6b03df664b8f5024a351d3389543ae (patch) | |
tree | ed3e4ae10b4a9621822e91e6972bbcde28843736 /drivers | |
parent | 60f60bf1bc45bef38568244f5c4e0d0f105c5032 (diff) | |
download | linux-3.10-292deb7a3b6b03df664b8f5024a351d3389543ae.tar.gz linux-3.10-292deb7a3b6b03df664b8f5024a351d3389543ae.tar.bz2 linux-3.10-292deb7a3b6b03df664b8f5024a351d3389543ae.zip |
drm/nv50-nvc0: tidy evo object creation some more
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_display.h | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_evo.c | 108 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_evo.h | 6 |
3 files changed, 62 insertions, 59 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_display.h b/drivers/gpu/drm/nouveau/nv50_display.h index a51b8853a92..3f5a3d54359 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.h +++ b/drivers/gpu/drm/nouveau/nv50_display.h @@ -62,4 +62,11 @@ void nv50_display_destroy(struct drm_device *dev); int nv50_crtc_blank(struct nouveau_crtc *, bool blank); int nv50_crtc_set_clock(struct drm_device *, int head, int pclk); +int nv50_evo_init(struct drm_device *dev); +void nv50_evo_fini(struct drm_device *dev); +void nv50_evo_dmaobj_init(struct nouveau_gpuobj *, u32 memtype, u64 base, + u64 size); +int nv50_evo_dmaobj_new(struct nouveau_channel *, u32 handle, u32 memtype, + u64 base, u64 size, struct nouveau_gpuobj **); + #endif /* __NV50_DISPLAY_H__ */ diff --git a/drivers/gpu/drm/nouveau/nv50_evo.c b/drivers/gpu/drm/nouveau/nv50_evo.c index eea96205fca..b70208e981f 100644 --- a/drivers/gpu/drm/nouveau/nv50_evo.c +++ b/drivers/gpu/drm/nouveau/nv50_evo.c @@ -48,12 +48,34 @@ nv50_evo_channel_del(struct nouveau_channel **pevo) kfree(evo); } +void +nv50_evo_dmaobj_init(struct nouveau_gpuobj *obj, u32 memtype, u64 base, u64 size) +{ + struct drm_nouveau_private *dev_priv = obj->dev->dev_private; + u32 flags5; + + if (dev_priv->chipset < 0xc0) { + /* not supported on 0x50, specified in format mthd */ + if (dev_priv->chipset == 0x50) + memtype = 0; + flags5 = 0x00010000; + } else { + if (memtype & 0x80000000) + flags5 = 0x00000000; /* large pages */ + else + flags5 = 0x00020000; + } + + nv50_gpuobj_dma_init(obj, 0, 0x3d, base, size, NV_MEM_TARGET_VRAM, + NV_MEM_ACCESS_RW, (memtype >> 8) & 0xff, 0); + nv_wo32(obj, 0x14, flags5); + dev_priv->engine.instmem.flush(obj->dev); +} + int -nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name, - u32 tile_flags, u32 magic_flags, u32 offset, u32 limit, - u32 flags5) +nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 handle, u32 memtype, + u64 base, u64 size, struct nouveau_gpuobj **pobj) { - struct drm_nouveau_private *dev_priv = evo->dev->dev_private; struct nv50_display *disp = nv50_display(evo->dev); struct nouveau_gpuobj *obj = NULL; int ret; @@ -63,21 +85,17 @@ nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name, return ret; obj->engine = NVOBJ_ENGINE_DISPLAY; - nv_wo32(obj, 0, (tile_flags << 22) | (magic_flags << 16) | class); - nv_wo32(obj, 4, limit); - nv_wo32(obj, 8, offset); - nv_wo32(obj, 12, 0x00000000); - nv_wo32(obj, 16, 0x00000000); - nv_wo32(obj, 20, flags5); - dev_priv->engine.instmem.flush(evo->dev); + nv50_evo_dmaobj_init(obj, memtype, base, size); - ret = nouveau_ramht_insert(evo, name, obj); - nouveau_gpuobj_ref(NULL, &obj); - if (ret) { - return ret; - } + ret = nouveau_ramht_insert(evo, handle, obj); + if (ret) + goto out; - return 0; + if (pobj) + nouveau_gpuobj_ref(obj, pobj); +out: + nouveau_gpuobj_ref(NULL, &obj); + return ret; } static int @@ -265,49 +283,33 @@ nv50_evo_create(struct drm_device *dev) if (ret) goto err; - ret = nv50_evo_dmaobj_new(disp->master, 0x3d, NvEvoSync, 0, 0x19, - disp->ntfy->vinst, disp->ntfy->vinst + - disp->ntfy->size, 0x00010000); + ret = nv50_evo_dmaobj_new(disp->master, NvEvoSync, 0x0000, + disp->ntfy->vinst, disp->ntfy->size, NULL); if (ret) goto err; /* create some default objects for the scanout memtypes we support */ - if (dev_priv->card_type >= NV_C0) { - ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0xfe, 0x19, - 0, 0xffffffff, 0x00000000); - if (ret) - goto err; - - ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19, - 0, dev_priv->vram_size, 0x00020000); - if (ret) - goto err; - - ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19, - 0, dev_priv->vram_size, 0x00000000); - if (ret) - goto err; - } else { - ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19, - 0, 0xffffffff, 0x00010000); - if (ret) - goto err; + ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM, 0x0000, + 0, dev_priv->vram_size, NULL); + if (ret) + goto err; - ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19, - 0, 0xffffffff, 0x00010000); - if (ret) - goto err; + ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM_LP, 0x80000000, + 0, dev_priv->vram_size, NULL); + if (ret) + goto err; - ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19, - 0, dev_priv->vram_size, 0x00010000); - if (ret) - goto err; + ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB32, 0x80000000 | + (dev_priv->chipset < 0xc0 ? 0x7a00 : 0xfe00), + 0, dev_priv->vram_size, NULL); + if (ret) + goto err; - ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19, - 0, dev_priv->vram_size, 0x00010000); - if (ret) - goto err; - } + ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB16, 0x80000000 | + (dev_priv->chipset < 0xc0 ? 0x7000 : 0xfe00), + 0, dev_priv->vram_size, NULL); + if (ret) + goto err; return 0; diff --git a/drivers/gpu/drm/nouveau/nv50_evo.h b/drivers/gpu/drm/nouveau/nv50_evo.h index 95c411905b1..e6b069fec0b 100644 --- a/drivers/gpu/drm/nouveau/nv50_evo.h +++ b/drivers/gpu/drm/nouveau/nv50_evo.h @@ -27,12 +27,6 @@ #ifndef __NV50_EVO_H__ #define __NV50_EVO_H__ -int nv50_evo_init(struct drm_device *dev); -void nv50_evo_fini(struct drm_device *dev); -int nv50_evo_dmaobj_new(struct nouveau_channel *, u32 class, u32 name, - u32 tile_flags, u32 magic_flags, - u32 offset, u32 limit, u32 flags5); - #define NV50_EVO_UPDATE 0x00000080 #define NV50_EVO_UNK84 0x00000084 #define NV50_EVO_UNK84_NOTIFY 0x40000000 |