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| author | Eric Anholt <eric@anholt.net> | 2010-03-08 23:41:55 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-03-17 12:59:32 -0700 |
| commit | 71cf39b117d5aa817a4693f4478397e6b04bee25 (patch) | |
| tree | 7c7dd6fb84629e4fbc7b4c70f1b55889bcf0d200 /drivers/gpu | |
| parent | 4967790112b284f276c5065dc724f7340a2fd7a5 (diff) | |
| download | linux-3.10-71cf39b117d5aa817a4693f4478397e6b04bee25.tar.gz linux-3.10-71cf39b117d5aa817a4693f4478397e6b04bee25.tar.bz2 linux-3.10-71cf39b117d5aa817a4693f4478397e6b04bee25.zip | |
drm/i915: Enable VS timer dispatch.
This could resolve HW deadlocks where a unit downstream of the VS is
waiting for more input, the VS has one vertex queued up but not
dispatched because it hopes to get one more vertex for 2x4 dispatch,
and software isn't handing more vertices down because it's waiting for
rendering to complete. The B-Spec says you should always have this
bit set.
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e52a277814c..134973f7706 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4725,6 +4725,11 @@ i915_gem_init_ringbuffer(struct drm_device *dev) ring->space += ring->Size; } + if (IS_I9XX(dev) && !IS_GEN3(dev)) { + I915_WRITE(MI_MODE, + (VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH); + } + return 0; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1fcc4c9efc0..2720bc2cd67 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -298,6 +298,10 @@ #define INSTDONE 0x02090 #define NOPID 0x02094 #define HWSTAM 0x02098 + +#define MI_MODE 0x0209c +# define VS_TIMER_DISPATCH (1 << 6) + #define SCPD0 0x0209c /* 915+ only */ #define IER 0x020a0 #define IIR 0x020a4 |