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| author | Ben Skeggs <bskeggs@redhat.com> | 2012-08-06 21:56:18 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2012-10-03 13:13:02 +1000 |
| commit | 6fa8e62937687cb2db10d0e7c7f91eb73a20365c (patch) | |
| tree | 10ec1875e369a3197809df73a67c1468a5d6dde7 /drivers/gpu/drm | |
| parent | 49981046e3dc2f934663548a270d4bf1a4534bb9 (diff) | |
| download | linux-3.10-6fa8e62937687cb2db10d0e7c7f91eb73a20365c.tar.gz linux-3.10-6fa8e62937687cb2db10d0e7c7f91eb73a20365c.tar.bz2 linux-3.10-6fa8e62937687cb2db10d0e7c7f91eb73a20365c.zip | |
drm/nv84/fifo: mask only the engine we're waiting on for channel unload
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c index d3b0356a428..694a9bbaa02 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c @@ -81,14 +81,15 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend, struct nv50_fifo_priv *priv = (void *)parent->engine; struct nv50_fifo_base *base = (void *)parent->parent; struct nv50_fifo_chan *chan = (void *)parent; - u32 addr; + u32 addr, save, engn; + bool done; switch (nv_engidx(object->engine)) { case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0020; break; - case NVDEV_ENGINE_MPEG : addr = 0x0060; break; - case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break; - case NVDEV_ENGINE_COPY0: addr = 0x00c0; break; + case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break; + case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break; + case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break; + case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break; default: return -EINVAL; } @@ -101,8 +102,11 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend, nv_wo32(base->eng, addr + 0x14, 0x00000000); bar->flush(bar); + save = nv_mask(priv, 0x002520, 0x0000003f, 1 << engn); nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12); - if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) { + done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff); + nv_wr32(priv, 0x002520, save); + if (!done) { nv_error(priv, "channel %d unload timeout\n", chan->base.chid); if (suspend) return -EBUSY; |