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author | Paul Mundt <lethal@linux-sh.org> | 2007-03-05 19:46:47 +0900 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2007-03-05 19:46:47 +0900 |
commit | 39e688a94b94eaba768b1494e19e96f828fc2688 (patch) | |
tree | 706ce255a95d0705241beafb8354fb7253a24af4 /arch/sh/mm/tlb-sh4.c | |
parent | c87a7111349891043cb0a62b0ba745264d4b600a (diff) | |
download | linux-3.10-39e688a94b94eaba768b1494e19e96f828fc2688.tar.gz linux-3.10-39e688a94b94eaba768b1494e19e96f828fc2688.tar.bz2 linux-3.10-39e688a94b94eaba768b1494e19e96f828fc2688.zip |
sh: Revert lazy dcache writeback changes.
These ended up causing too many problems on older parts,
revert for now..
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/mm/tlb-sh4.c')
-rw-r--r-- | arch/sh/mm/tlb-sh4.c | 68 |
1 files changed, 67 insertions, 1 deletions
diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c index 221e7095473..f74cf667c8f 100644 --- a/arch/sh/mm/tlb-sh4.c +++ b/arch/sh/mm/tlb-sh4.c @@ -8,9 +8,74 @@ * * Released under the terms of the GNU GPL v2.0. */ -#include <linux/io.h> +#include <linux/signal.h> +#include <linux/sched.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/string.h> +#include <linux/types.h> +#include <linux/ptrace.h> +#include <linux/mman.h> +#include <linux/mm.h> +#include <linux/smp.h> +#include <linux/smp_lock.h> +#include <linux/interrupt.h> + #include <asm/system.h> +#include <asm/io.h> +#include <asm/uaccess.h> +#include <asm/pgalloc.h> #include <asm/mmu_context.h> +#include <asm/cacheflush.h> + +void update_mmu_cache(struct vm_area_struct * vma, + unsigned long address, pte_t pte) +{ + unsigned long flags; + unsigned long pteval; + unsigned long vpn; + struct page *page; + unsigned long pfn; + + /* Ptrace may call this routine. */ + if (vma && current->active_mm != vma->vm_mm) + return; + + pfn = pte_pfn(pte); + if (pfn_valid(pfn)) { + page = pfn_to_page(pfn); + if (!test_bit(PG_mapped, &page->flags)) { + unsigned long phys = pte_val(pte) & PTE_PHYS_MASK; + __flush_wback_region((void *)P1SEGADDR(phys), PAGE_SIZE); + __set_bit(PG_mapped, &page->flags); + } + } + + local_irq_save(flags); + + /* Set PTEH register */ + vpn = (address & MMU_VPN_MASK) | get_asid(); + ctrl_outl(vpn, MMU_PTEH); + + pteval = pte_val(pte); + + /* Set PTEA register */ + if (cpu_data->flags & CPU_HAS_PTEA) + /* TODO: make this look less hacky */ + ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA); + + /* Set PTEL register */ + pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */ +#ifdef CONFIG_SH_WRITETHROUGH + pteval |= _PAGE_WT; +#endif + /* conveniently, we want all the software flags to be 0 anyway */ + ctrl_outl(pteval, MMU_PTEL); + + /* Load the TLB */ + asm volatile("ldtlb": /* no output */ : /* no input */ : "memory"); + local_irq_restore(flags); +} void local_flush_tlb_one(unsigned long asid, unsigned long page) { @@ -28,3 +93,4 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page) ctrl_outl(data, addr); back_to_P1(); } + |