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authorPaul Mundt <lethal@linux-sh.org>2010-04-05 12:21:09 +0900
committerPaul Mundt <lethal@linux-sh.org>2010-04-05 12:21:09 +0900
commit94a46d3cde81fc82eef2105fcb5c9e6e31bac0f7 (patch)
tree445ff43779938b539e0799e81c90b85bbee552cd /arch/sh/mm/tlb-sh3.c
parent720fcb36ac1aa2df2c54c170253b6b29600cbefc (diff)
parentdb217dece3003df0841bacf9556b5c06aa097dae (diff)
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Merge branch 'sh/stable-updates'
Diffstat (limited to 'arch/sh/mm/tlb-sh3.c')
-rw-r--r--arch/sh/mm/tlb-sh3.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c
index 4f5f7cbdd50..7a940dbfc2e 100644
--- a/arch/sh/mm/tlb-sh3.c
+++ b/arch/sh/mm/tlb-sh3.c
@@ -77,3 +77,22 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
for (i = 0; i < ways; i++)
__raw_writel(data, addr + (i << 8));
}
+
+void local_flush_tlb_all(void)
+{
+ unsigned long flags, status;
+
+ /*
+ * Flush all the TLB.
+ *
+ * Write to the MMU control register's bit:
+ * TF-bit for SH-3, TI-bit for SH-4.
+ * It's same position, bit #2.
+ */
+ local_irq_save(flags);
+ status = __raw_readl(MMUCR);
+ status |= 0x04;
+ __raw_writel(status, MMUCR);
+ ctrl_barrier();
+ local_irq_restore(flags);
+}