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| author | Frank van Maarseveen <frankvm@frankvm.com> | 2005-09-09 13:01:46 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-09-09 13:57:29 -0700 |
| commit | 99cc2192132ab28c495d015ed2e95dc29e2a27ad (patch) | |
| tree | 4cc085c47f0824f4b028d6d31eab0f63765615c0 /arch/ppc | |
| parent | 83f7da8acd81354e921ff12d6efbeae5b1a5d6a4 (diff) | |
| download | linux-3.10-99cc2192132ab28c495d015ed2e95dc29e2a27ad.tar.gz linux-3.10-99cc2192132ab28c495d015ed2e95dc29e2a27ad.tar.bz2 linux-3.10-99cc2192132ab28c495d015ed2e95dc29e2a27ad.zip | |
[PATCH] ppc32: Correct an instruction in the boot code
In the flush and invalidate bootcode on PPC4xx we were accidentally using
the wrong instruction. Use cmplw, which reads from a register like we
want.
Signed-off-by: Tom Rini <trini@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc')
| -rw-r--r-- | arch/ppc/boot/common/util.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/ppc/boot/common/util.S b/arch/ppc/boot/common/util.S index 47e641455bc..c96c9f80521 100644 --- a/arch/ppc/boot/common/util.S +++ b/arch/ppc/boot/common/util.S @@ -252,7 +252,7 @@ _GLOBAL(flush_instruction_cache) 1: dcbf r0,r3 # Flush the data cache icbi r0,r3 # Invalidate the instruction cache addi r3,r3,0x10 # Increment by one cache line - cmplwi cr0,r3,r4 # Are we at the end yet? + cmplw cr0,r3,r4 # Are we at the end yet? blt 1b # No, keep flushing and invalidating #else /* Enable, invalidate and then disable the L1 icache/dcache. */ |