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author | Ingo Molnar <mingo@elte.hu> | 2008-07-18 19:53:16 +0200 |
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committer | Ingo Molnar <mingo@elte.hu> | 2008-07-18 19:53:16 +0200 |
commit | 9b610fda0df5d0f0b0c64242e37441ad1b384aac (patch) | |
tree | 0ea14b15f2e6546f37fe18d8ac3dc83077ec0e55 /arch/ppc/platforms/4xx/bubinga.h | |
parent | b8f8c3cf0a4ac0632ec3f0e15e9dc0c29de917af (diff) | |
parent | 5b664cb235e97afbf34db9c4d77f08ebd725335e (diff) | |
download | linux-3.10-9b610fda0df5d0f0b0c64242e37441ad1b384aac.tar.gz linux-3.10-9b610fda0df5d0f0b0c64242e37441ad1b384aac.tar.bz2 linux-3.10-9b610fda0df5d0f0b0c64242e37441ad1b384aac.zip |
Merge branch 'linus' into timers/nohz
Diffstat (limited to 'arch/ppc/platforms/4xx/bubinga.h')
-rw-r--r-- | arch/ppc/platforms/4xx/bubinga.h | 54 |
1 files changed, 0 insertions, 54 deletions
diff --git a/arch/ppc/platforms/4xx/bubinga.h b/arch/ppc/platforms/4xx/bubinga.h deleted file mode 100644 index 5c408060eb3..00000000000 --- a/arch/ppc/platforms/4xx/bubinga.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Bubinga board definitions - * - * Copyright (c) 2005 DENX Software Engineering - * Stefan Roese <sr@denx.de> - * - * Based on original work by - * SAW (IBM) - * 2003 (c) MontaVista Softare Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifdef __KERNEL__ -#ifndef __BUBINGA_H__ -#define __BUBINGA_H__ - -#include <platforms/4xx/ibm405ep.h> -#include <asm/ppcboot.h> - -/* Memory map for the Bubinga board. - * Generic 4xx plus RTC. - */ - -#define BUBINGA_RTC_PADDR ((uint)0xf0000000) -#define BUBINGA_RTC_VADDR BUBINGA_RTC_PADDR -#define BUBINGA_RTC_SIZE ((uint)8*1024) - -/* The UART clock is based off an internal clock - - * define BASE_BAUD based on the internal clock and divider(s). - * Since BASE_BAUD must be a constant, we will initialize it - * using clock/divider values which OpenBIOS initializes - * for typical configurations at various CPU speeds. - * The base baud is calculated as (FWDA / EXT UART DIV / 16) - */ -#define BASE_BAUD 0 - -/* Flash */ -#define PPC40x_FPGA_BASE 0xF0300000 -#define PPC40x_FPGA_REG_OFFS 1 /* offset to flash map reg */ -#define PPC40x_FLASH_ONBD_N(x) (x & 0x02) -#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01) -#define PPC40x_FLASH_LOW 0xFFF00000 -#define PPC40x_FLASH_HIGH 0xFFF80000 -#define PPC40x_FLASH_SIZE 0x80000 - -#define PPC4xx_MACHINE_NAME "IBM Bubinga" - -#endif /* __BUBINGA_H__ */ -#endif /* __KERNEL__ */ |