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| author | Ralf Baechle <ralf@linux-mips.org> | 2012-10-17 00:39:09 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-12-12 16:48:49 +0100 |
| commit | f65aad41772f6a0022e9763fe06f47604449964c (patch) | |
| tree | 701d6ea74ac0c41f008c5554d876945fe4caf512 /arch/mips/pci | |
| parent | aa1762f49c81a14d0453e4f67f922e4f155510a3 (diff) | |
| download | linux-3.10-f65aad41772f6a0022e9763fe06f47604449964c.tar.gz linux-3.10-f65aad41772f6a0022e9763fe06f47604449964c.tar.bz2 linux-3.10-f65aad41772f6a0022e9763fe06f47604449964c.zip | |
MIPS: Cavium: Add EDAC support.
Drivers for EDAC on Cavium. Supported subsystems are:
o CPU primary caches. These are parity protected only, so only error
reporting.
o Second level cache - ECC protected, provides SECDED.
o Memory: ECC / SECDEC if used with suitable DRAM modules. The driver will
will only initialize if ECC is enabled on a system so is safe to run on
non-ECC memory.
o PCI: Parity error reporting
Since it is very hard to test this sort of code the implementation is very
conservative and uses polling where possible for now.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Reviewed-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'arch/mips/pci')
| -rw-r--r-- | arch/mips/pci/pci-octeon.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 4b0c347d7a8..8eb2ee345d0 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -11,6 +11,7 @@ #include <linux/interrupt.h> #include <linux/time.h> #include <linux/delay.h> +#include <linux/platform_device.h> #include <linux/swiotlb.h> #include <asm/time.h> @@ -704,6 +705,9 @@ static int __init octeon_pci_setup(void) */ cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1); + if (IS_ERR(platform_device_register_simple("co_pci_edac", 0, NULL, 0))) + pr_err("Registation of co_pci_edac failed!\n"); + octeon_pci_dma_init(); return 0; |