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| author | David Daney <david.daney@cavium.com> | 2012-04-03 13:44:18 -0700 |
|---|---|---|
| committer | David Daney <david.daney@cavium.com> | 2012-08-31 10:46:53 -0700 |
| commit | c5aa59e88fe415b1c44d389387ec1e26450e672c (patch) | |
| tree | 196de0c85f72170f6280de322cfa4c482efb2e20 /arch/mips/include/asm/octeon/cvmx-l2t-defs.h | |
| parent | 5cf02e5554a429268e53fd4a19806644de73a82f (diff) | |
| download | linux-3.10-c5aa59e88fe415b1c44d389387ec1e26450e672c.tar.gz linux-3.10-c5aa59e88fe415b1c44d389387ec1e26450e672c.tar.bz2 linux-3.10-c5aa59e88fe415b1c44d389387ec1e26450e672c.zip | |
MIPS: OCTEON: Update register definitions.
Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX.
Add little-endian register layouts.
Patch cvmx-interrupt-rsl.c for changed definition.
Signed-off-by: David Daney <david.daney@cavium.com>
Diffstat (limited to 'arch/mips/include/asm/octeon/cvmx-l2t-defs.h')
| -rw-r--r-- | arch/mips/include/asm/octeon/cvmx-l2t-defs.h | 105 |
1 files changed, 104 insertions, 1 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h index 873968f55ee..83ce22c080e 100644 --- a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -33,6 +33,7 @@ union cvmx_l2t_err { uint64_t u64; struct cvmx_l2t_err_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t fadru:1; uint64_t lck_intena2:1; @@ -47,8 +48,25 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:10; + uint64_t fset:3; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t fadru:1; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_l2t_err_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -64,8 +82,26 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:8; + uint64_t reserved_19_20:2; + uint64_t fset:2; + uint64_t reserved_23_23:1; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn30xx; struct cvmx_l2t_err_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -81,8 +117,26 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:9; + uint64_t reserved_20_20:1; + uint64_t fset:2; + uint64_t reserved_23_23:1; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn31xx; struct cvmx_l2t_err_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -96,9 +150,25 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:10; + uint64_t fset:3; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn38xx; struct cvmx_l2t_err_cn38xx cn38xxp2; struct cvmx_l2t_err_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -113,8 +183,25 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:7; + uint64_t reserved_18_20:3; + uint64_t fset:3; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn50xx; struct cvmx_l2t_err_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -129,6 +216,22 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:9; + uint64_t reserved_20_20:1; + uint64_t fset:3; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn52xx; struct cvmx_l2t_err_cn52xx cn52xxp1; struct cvmx_l2t_err_s cn56xx; |