diff options
| author | Steven King <sfking@fdwdc.com> | 2012-06-08 14:15:29 -0700 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2012-07-16 09:59:21 +1000 |
| commit | 32234328e24a38d8f9c42bd534ebfbd73fce8435 (patch) | |
| tree | 0ebce34be6c946a05b53ab449fb644f8c3bb81aa /arch/m68k | |
| parent | bea8bcb12da09bd35cdada395d0d0db1aee2ba4c (diff) | |
| download | linux-3.10-32234328e24a38d8f9c42bd534ebfbd73fce8435.tar.gz linux-3.10-32234328e24a38d8f9c42bd534ebfbd73fce8435.tar.bz2 linux-3.10-32234328e24a38d8f9c42bd534ebfbd73fce8435.zip | |
m68knommu: add definitions for the third interrupt controller on devices that don't have a third interrupt controller.
Extending the interrupt controller code in intc-simr.c to support the third
interrupt controller on the m5441x means we need to add defines (as 0) for the
third interrupt controller on devices that don't have a third interrupt
controller.
Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
| -rw-r--r-- | arch/m68k/include/asm/m520xsim.h | 3 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m532xsim.h | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index 5a8b5e4da12..b1bc76f1dec 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -42,6 +42,9 @@ #define MCFINTC1_SIMR (0) #define MCFINTC1_CIMR (0) #define MCFINTC1_ICR0 (0) +#define MCFINTC2_SIMR (0) +#define MCFINTC2_CIMR (0) +#define MCFINTC2_ICR0 (0) #define MCFINT_VECBASE 64 #define MCFINT_UART0 26 /* Interrupt number for UART0 */ diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index 29b66e21413..8d860200a2f 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -82,6 +82,9 @@ #define MCFINTC1_SIMR 0xFC04C01C #define MCFINTC1_CIMR 0xFC04C01D #define MCFINTC1_ICR0 0xFC04C040 +#define MCFINTC2_SIMR (0) +#define MCFINTC2_CIMR (0) +#define MCFINTC2_ICR0 (0) #define MCFSIM_ICR_TIMER1 (0xFC048040+32) #define MCFSIM_ICR_TIMER2 (0xFC048040+33) |