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| author | Rob Herring <rob.herring@calxeda.com> | 2012-01-09 15:39:19 -0600 |
|---|---|---|
| committer | Rob Herring <rob.herring@calxeda.com> | 2012-01-16 08:36:04 -0600 |
| commit | f7597c02a2e6fada7a065b03efe283ae7ef0e0bc (patch) | |
| tree | 56fef0a1d6c8c16840c5a3f1fe7171996f6605e6 /arch/arm | |
| parent | 09f759f66b82bbfe21e165acf0e57e7725466312 (diff) | |
| download | linux-3.10-f7597c02a2e6fada7a065b03efe283ae7ef0e0bc.tar.gz linux-3.10-f7597c02a2e6fada7a065b03efe283ae7ef0e0bc.tar.bz2 linux-3.10-f7597c02a2e6fada7a065b03efe283ae7ef0e0bc.zip | |
ARM: exynos: remove incorrect BSYM usage
BSYM macro is only needed for assembly files and its usage in c files is
wrong, so remove it. The linker will correctly set bit 0 for Thumb2
kernels.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Dave Martin <dave.martin@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-exynos/headsmp.S | 2 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/platsmp.c | 5 |
2 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S index 3cdeb364754..5364d4bfa8b 100644 --- a/arch/arm/mach-exynos/headsmp.S +++ b/arch/arm/mach-exynos/headsmp.S @@ -36,6 +36,8 @@ pen: ldr r7, [r6] * should now contain the SVC stack for this core */ b secondary_startup +ENDPROC(exynos4_secondary_startup) + .align 2 1: .long . .long pen_release diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 69ffb2fb387..b89bfa5b6b7 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -24,7 +24,6 @@ #include <asm/cacheflush.h> #include <asm/hardware/gic.h> #include <asm/smp_scu.h> -#include <asm/unified.h> #include <mach/hardware.h> #include <mach/regs-clock.h> @@ -163,7 +162,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) while (time_before(jiffies, timeout)) { smp_rmb(); - __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), + __raw_writel(virt_to_phys(exynos4_secondary_startup), CPU1_BOOT_REG); gic_raise_softirq(cpumask_of(cpu), 1); @@ -218,6 +217,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * until it receives a soft interrupt, and then the * secondary CPU branches to this address. */ - __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), + __raw_writel(virt_to_phys(exynos4_secondary_startup), CPU1_BOOT_REG); } |