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| author | Ben Dooks <ben-linux@fluff.org> | 2009-11-30 01:10:57 +0000 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2010-01-15 17:10:08 +0900 |
| commit | f9c4f1e4ddf40103dcf85e23d00230ab8ece2a89 (patch) | |
| tree | b8e3e318ac7991daf951d5dca05cdaf85811f806 /arch/arm/plat-s3c64xx | |
| parent | 70792bcfad5f4817fc067b7fdb0541d8b13b5502 (diff) | |
| download | linux-3.10-f9c4f1e4ddf40103dcf85e23d00230ab8ece2a89.tar.gz linux-3.10-f9c4f1e4ddf40103dcf85e23d00230ab8ece2a89.tar.bz2 linux-3.10-f9c4f1e4ddf40103dcf85e23d00230ab8ece2a89.zip | |
ARM: S3C64XX: Cleanup common init code in s3c6400-clock.c
Remove the four fields from clksrc_clk.clk which are always the same
and init them when the clock is registered. This helps remove the amount
of repeated code.
This is a re-work of Harald Welte's clock changes for the latest kernel.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c64xx')
| -rw-r--r-- | arch/arm/plat-s3c64xx/s3c6400-clock.c | 49 |
1 files changed, 5 insertions, 44 deletions
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index ffd56deb9e8..aba08c7d312 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -360,10 +360,6 @@ static struct clksrc_clk clk_mmc0 = { .id = 0, .ctrlbit = S3C_CLKCON_SCLK_MMC0, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_MMC0_SHIFT, .mask = S3C6400_CLKSRC_MMC0_MASK, @@ -378,10 +374,6 @@ static struct clksrc_clk clk_mmc1 = { .id = 1, .ctrlbit = S3C_CLKCON_SCLK_MMC1, .enable = s3c64xx_sclk_ctrl, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .set_parent = s3c64xx_setparent_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_MMC1_SHIFT, .mask = S3C6400_CLKSRC_MMC1_MASK, @@ -396,10 +388,6 @@ static struct clksrc_clk clk_mmc2 = { .id = 2, .ctrlbit = S3C_CLKCON_SCLK_MMC2, .enable = s3c64xx_sclk_ctrl, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .set_parent = s3c64xx_setparent_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_MMC2_SHIFT, .mask = S3C6400_CLKSRC_MMC2_MASK, @@ -414,10 +402,6 @@ static struct clksrc_clk clk_usbhost = { .id = -1, .ctrlbit = S3C_CLKCON_SCLK_UHOST, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_UHOST_SHIFT, .mask = S3C6400_CLKSRC_UHOST_MASK, @@ -432,10 +416,6 @@ static struct clksrc_clk clk_uart_uclk1 = { .id = -1, .ctrlbit = S3C_CLKCON_SCLK_UART, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_UART_SHIFT, .mask = S3C6400_CLKSRC_UART_MASK, @@ -452,10 +432,6 @@ static struct clksrc_clk clk_spi0 = { .id = 0, .ctrlbit = S3C_CLKCON_SCLK_SPI0, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_SPI0_SHIFT, .mask = S3C6400_CLKSRC_SPI0_MASK, @@ -470,10 +446,6 @@ static struct clksrc_clk clk_spi1 = { .id = 1, .ctrlbit = S3C_CLKCON_SCLK_SPI1, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_SPI1_SHIFT, .mask = S3C6400_CLKSRC_SPI1_MASK, @@ -516,10 +488,6 @@ static struct clksrc_clk clk_audio0 = { .id = 0, .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_AUDIO0_SHIFT, .mask = S3C6400_CLKSRC_AUDIO0_MASK, @@ -547,10 +515,6 @@ static struct clksrc_clk clk_audio1 = { .id = 1, .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_AUDIO1_SHIFT, .mask = S3C6400_CLKSRC_AUDIO1_MASK, @@ -565,10 +529,6 @@ static struct clksrc_clk clk_irda = { .id = 0, .ctrlbit = S3C_CLKCON_SCLK_IRDA, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_IRDA_SHIFT, .mask = S3C6400_CLKSRC_IRDA_MASK, @@ -592,10 +552,6 @@ static struct clksrc_clk clk_camif = { .id = -1, .ctrlbit = S3C_CLKCON_SCLK_CAM, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = 0, .mask = 0, @@ -637,6 +593,11 @@ static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk) return; } + clk->clk.get_rate = s3c64xx_getrate_clksrc; + clk->clk.set_rate = s3c64xx_setrate_clksrc; + clk->clk.set_parent = s3c64xx_setparent_clksrc; + clk->clk.round_rate = s3c64xx_roundrate_clksrc; + clk->clk.parent = srcs->sources[clksrc]; printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", |