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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2009-12-11 16:16:35 -0800
committerTony Lindgren <tony@atomide.com>2009-12-11 16:16:35 -0800
commit942e2c9e529a57ce2bb1cf984d58f88d9b6e77e5 (patch)
tree2892251635eafe9fa4a323a698d501c7ce9cb178 /arch/arm/plat-omap
parenta7c3ae2cb6d144bdf6c582898d2368f5f91a1775 (diff)
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OMAP4: AuxCoreBoot registers only accessible in secure mode
The AuxCoreBoot0 and AuxCoreBoot1 can be only accessed in secure mode. Replace the current code with secure monitor API's to access/modify these registers. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/include/plat/smp.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index dcaa8fde706..8983d54c4fd 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -28,6 +28,8 @@
/* Needed for secondary core boot */
extern void omap_secondary_startup(void);
+extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
+extern void omap_auxcoreboot_addr(u32 cpu_addr);
/*
* We use Soft IRQ1 as the IPI