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| author | Josh Cartwright <josh.cartwright@ni.com> | 2012-10-17 19:46:49 -0500 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2012-10-29 08:31:01 +0100 |
| commit | f447ed2dbc844d645ef8bf82cc04281fa4163aed (patch) | |
| tree | d28c42f459404145716e969c87082487a6669dad /arch/arm/mach-zynq | |
| parent | 8f0d8163b50e01f398b14bcd4dc039ac5ab18d64 (diff) | |
| download | linux-3.10-f447ed2dbc844d645ef8bf82cc04281fa4163aed.tar.gz linux-3.10-f447ed2dbc844d645ef8bf82cc04281fa4163aed.tar.bz2 linux-3.10-f447ed2dbc844d645ef8bf82cc04281fa4163aed.zip | |
zynq: use GIC device tree bindings
The Zynq uses the cortex-a9-gic. This eliminates the need to hardcode
register addresses.
Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Cc: John Linn <john.linn@xilinx.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/mach-zynq')
| -rw-r--r-- | arch/arm/mach-zynq/common.c | 7 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/include/mach/zynq_soc.h | 2 |
2 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index ab5cfddc0d7..d73963b422a 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -55,12 +55,17 @@ static void __init xilinx_init_machine(void) of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); } +static struct of_device_id irq_match[] __initdata = { + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, + { } +}; + /** * xilinx_irq_init() - Interrupt controller initialization for the GIC. */ static void __init xilinx_irq_init(void) { - gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE); + of_irq_init(irq_match); } /* The minimum devices needed to be mapped before the VM system is up and diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h index d0d3f8fb06d..3d1c6a6a8fe 100644 --- a/arch/arm/mach-zynq/include/mach/zynq_soc.h +++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h @@ -35,8 +35,6 @@ #define TTC0_BASE IOMEM(TTC0_VIRT) #define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) -#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100) -#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000) #define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT) /* |