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| author | Shiraz Hashim <shiraz.hashim@st.com> | 2012-03-07 17:00:52 +0530 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2012-03-27 00:46:19 +0100 |
| commit | 02bfc4ebbd2532440fadd78076f3a51e0ae89f7f (patch) | |
| tree | 51317b0b1bce317b83c4b78d33ba02551a889e6e /arch/arm/mach-u300 | |
| parent | b2acc92e144336dd29e30dc5d26439355be750b6 (diff) | |
| download | linux-3.10-02bfc4ebbd2532440fadd78076f3a51e0ae89f7f.tar.gz linux-3.10-02bfc4ebbd2532440fadd78076f3a51e0ae89f7f.tar.bz2 linux-3.10-02bfc4ebbd2532440fadd78076f3a51e0ae89f7f.zip | |
mtd: fsmc: Move ALE, CLE defines to their respective platform
Address Latch Enable (ALE) and Command Latch Enable (CLE) defines are
platform specific and were wrongly put in driver specific fsmc.h file.
Move such defines to their respective platform.
Also instead of relying on fsmc driver, pass ALE, CLE offsets explicitly
from individual platform.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'arch/arm/mach-u300')
| -rw-r--r-- | arch/arm/mach-u300/core.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-u300/include/mach/u300-regs.h | 5 |
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index b4c6926a700..9c3bafd48cd 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -1574,6 +1574,8 @@ static struct fsmc_nand_platform_data nand_platform_data = { .nr_partitions = ARRAY_SIZE(u300_partitions), .options = NAND_SKIP_BBTSCAN, .width = FSMC_NAND_BW8, + .ale_off = PLAT_NAND_ALE, + .cle_off = PLAT_NAND_CLE, }; static struct platform_device nand_device = { diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h index 035fdc9dbdb..b9701fb86db 100644 --- a/arch/arm/mach-u300/include/mach/u300-regs.h +++ b/arch/arm/mach-u300/include/mach/u300-regs.h @@ -30,6 +30,11 @@ /* NFIF */ #define U300_NAND_IF_PHYS_BASE 0x9f800000 +/* ALE, CLE offset for FSMC NAND */ +#define PLAT_NAND_CLE (1 << 16) +#define PLAT_NAND_ALE (1 << 17) + + /* AHB Peripherals */ #define U300_AHB_PER_PHYS_BASE 0xa0000000 #define U300_AHB_PER_VIRT_BASE 0xff010000 |