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| author | Rob Herring <rob.herring@calxeda.com> | 2012-08-31 00:03:46 -0500 |
|---|---|---|
| committer | Rob Herring <rob.herring@calxeda.com> | 2012-09-14 09:22:00 -0500 |
| commit | 91a9fec022f5d98835e27d5307d487da3798040c (patch) | |
| tree | fa2e41ee6bd1ae9ecd04e468c9e8918fc9891be8 /arch/arm/include | |
| parent | 01464226ac6089bd6a33f9899cc792c2355ebf39 (diff) | |
| download | linux-3.10-91a9fec022f5d98835e27d5307d487da3798040c.tar.gz linux-3.10-91a9fec022f5d98835e27d5307d487da3798040c.tar.bz2 linux-3.10-91a9fec022f5d98835e27d5307d487da3798040c.zip | |
ARM: move debug macros to common location
Based on suggestion by Russell King, create a common location for debug
macros and select the included debug macro file using config option.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/debug/icedcc.S | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/arch/arm/include/debug/icedcc.S b/arch/arm/include/debug/icedcc.S new file mode 100644 index 00000000000..43afcb021fa --- /dev/null +++ b/arch/arm/include/debug/icedcc.S @@ -0,0 +1,90 @@ +/* + * arch/arm/include/debug/icedcc.S + * + * Copyright (C) 1994-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + + @@ debug using ARM EmbeddedICE DCC channel + + .macro addruart, rp, rv, tmp + .endm + +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) + + .macro senduart, rd, rx + mcr p14, 0, \rd, c0, c5, 0 + .endm + + .macro busyuart, rd, rx +1001: + mrc p14, 0, \rx, c0, c1, 0 + tst \rx, #0x20000000 + beq 1001b + .endm + + .macro waituart, rd, rx + mov \rd, #0x2000000 +1001: + subs \rd, \rd, #1 + bmi 1002f + mrc p14, 0, \rx, c0, c1, 0 + tst \rx, #0x20000000 + bne 1001b +1002: + .endm + +#elif defined(CONFIG_CPU_XSCALE) + + .macro senduart, rd, rx + mcr p14, 0, \rd, c8, c0, 0 + .endm + + .macro busyuart, rd, rx +1001: + mrc p14, 0, \rx, c14, c0, 0 + tst \rx, #0x10000000 + beq 1001b + .endm + + .macro waituart, rd, rx + mov \rd, #0x10000000 +1001: + subs \rd, \rd, #1 + bmi 1002f + mrc p14, 0, \rx, c14, c0, 0 + tst \rx, #0x10000000 + bne 1001b +1002: + .endm + +#else + + .macro senduart, rd, rx + mcr p14, 0, \rd, c1, c0, 0 + .endm + + .macro busyuart, rd, rx +1001: + mrc p14, 0, \rx, c0, c0, 0 + tst \rx, #2 + beq 1001b + + .endm + + .macro waituart, rd, rx + mov \rd, #0x2000000 +1001: + subs \rd, \rd, #1 + bmi 1002f + mrc p14, 0, \rx, c0, c0, 0 + tst \rx, #2 + bne 1001b +1002: + .endm + +#endif /* CONFIG_CPU_V6 */ |