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| author | Marc Zyngier <Marc.Zyngier@arm.com> | 2012-10-06 17:03:17 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-10-09 12:11:34 +0100 |
| commit | 2a552d5e63d7fa602c9a9a0717008737f55625a6 (patch) | |
| tree | 0fbd4405ee99ba35cf508f67b01a932a89d71824 /arch/arm/include/asm/assembler.h | |
| parent | 648f3b69986b4d0ade57e59504a431b973ce2875 (diff) | |
| download | linux-3.10-2a552d5e63d7fa602c9a9a0717008737f55625a6.tar.gz linux-3.10-2a552d5e63d7fa602c9a9a0717008737f55625a6.tar.bz2 linux-3.10-2a552d5e63d7fa602c9a9a0717008737f55625a6.zip | |
ARM: 7549/1: HYP: fix boot on some ARM1136 cores
It appears that performing a "movs pc, lr" to force the kernel into
SVC mode on the OMAP2420 (ARM1136) prevents the platform from booting
correctly (change introduced in 80c59da [ARM: virt: allow the kernel
to be entered in HYP mode]).
While the reason it fails is not understood yet (the same code runs
fine on the OMAP2430, ARM1136 as well), partially revert that change
for platforms that do not enter in HYP mode, preserving the new
feature and restoring a working kernel on the OMAP2420.
Reported-by: Tony Lindgren <tony@atomide.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include/asm/assembler.h')
| -rw-r--r-- | arch/arm/include/asm/assembler.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 683a1e6b602..2ef95813fce 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -254,16 +254,17 @@ mov lr , \reg and lr , lr , #MODE_MASK cmp lr , #HYP_MODE - orr \reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT + orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT bic \reg , \reg , #MODE_MASK orr \reg , \reg , #SVC_MODE THUMB( orr \reg , \reg , #PSR_T_BIT ) - msr spsr_cxsf, \reg - adr lr, BSYM(2f) bne 1f + orr \reg, \reg, #PSR_A_BIT + adr lr, BSYM(2f) + msr spsr_cxsf, \reg __MSR_ELR_HYP(14) __ERET -1: movs pc, lr +1: msr cpsr_c, \reg 2: .endm |