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authorYounghwan Joo <yhwan.joo@samsung.com>2012-11-15 21:02:27 +0900
committerChanho Park <chanho61.park@samsung.com>2014-11-18 11:42:28 +0900
commitf1df704444245f759dc5b95630de4c41fa7f28c6 (patch)
tree617b8be809852f84ebb3cd727896d57fc2c366a1
parent08c864ea767228cb13300425aa3ba881e04c058a (diff)
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ARM: EXYNOS: change the value of EXYNOS4X12_ISP_LOWPWR
This patch is to fix the value of EXYNOS4X12_ISP_LOWPWR register to zero at AFTR mode. It ensure the sub selection mux of mcuisp400 and isp200 reset a default position after power down Signed-off-by: Younghwan Joo <yhwan.joo@samsung.com> Signed-off-by: JaeYong Shin <jy2.shin@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-rw-r--r--arch/arm/mach-exynos/pmu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 97d68852625..21cef18aff3 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -140,7 +140,7 @@ static struct exynos_pmu_conf exynos4x12_pmu_config[] = {
{ S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
- { S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_RESET_ISP_LOWPWR, { 0x0, 0x0, 0x0 } },
{ S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },