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authorShawn Guo <shawn.guo@linaro.org>2012-07-19 23:16:30 +0800
committerShawn Guo <shawn.guo@linaro.org>2012-11-16 14:18:53 +0800
commitd90df97863c7838847abd0f144c71db60aa00643 (patch)
tree0a467ce8312f4dbbf0e7792815b8be2be15dec36
parentc92503886c9e566708a05f92a99c9c3fe71f4348 (diff)
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ARM: imx: enable cpufreq for imx6q
It enables cpufreq support for imx6q with generic cpufreq-cpu0 driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi10
-rw-r--r--arch/arm/mach-imx/Kconfig3
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c1
3 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 255f56b124e..1565aea59eb 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -36,6 +36,14 @@
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&L2>;
+ operating-points = <
+ /* kHz uV */
+ 792000 1100000
+ 396000 950000
+ 198000 850000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ cpu0-supply = <&reg_cpu>;
};
cpu@1 {
@@ -447,7 +455,7 @@
anatop-max-voltage = <2750000>;
};
- regulator-vddcore@140 {
+ reg_cpu: regulator-vddcore@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "cpu";
regulator-min-microvolt = <725000>;
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index f1bf610e290..01bf72c56c0 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -829,6 +829,8 @@ config SOC_IMX53
config SOC_IMX6Q
bool "i.MX6 Quad support"
+ select ARCH_HAS_CPUFREQ
+ select ARCH_HAS_OPP
select ARM_CPU_SUSPEND if PM
select ARM_GIC
select COMMON_CLK
@@ -841,6 +843,7 @@ config SOC_IMX6Q
select MFD_SYSCON
select PINCTRL
select PINCTRL_IMX6Q
+ select PM_OPP if PM
help
This enables support for Freescale i.MX6 Quad processor.
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index e5a82bb95b5..5f9f5919dd7 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -406,6 +406,7 @@ int __init mx6q_clocks_init(void)
clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
clk_register_clkdev(clk[ahb], "ahb", NULL);
clk_register_clkdev(clk[cko1], "cko1", NULL);
+ clk_register_clkdev(clk[arm], NULL, "cpu0");
/*
* The gpmi needs 100MHz frequency in the EDO/Sync mode,