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| author | Ralf Baechle <ralf@linux-mips.org> | 2007-11-11 17:33:55 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-11-15 23:21:50 +0000 |
| commit | 8dfa741f146b39eb59ef2094e03f47079ca99eb0 (patch) | |
| tree | 823c790dff8619a3671c1a8a19671e020b9b4e2d | |
| parent | 622477533d3dc24845c847f386533f3c0e6a1be6 (diff) | |
| download | linux-3.10-8dfa741f146b39eb59ef2094e03f47079ca99eb0.tar.gz linux-3.10-8dfa741f146b39eb59ef2094e03f47079ca99eb0.tar.bz2 linux-3.10-8dfa741f146b39eb59ef2094e03f47079ca99eb0.zip | |
[MIPS] Sibyte: Stop timers before programming next even.
We have no guarantee by the generic time code that the timer is stopped
when the ->next_event method is called. Modifying the Timer Initial Count
register while the timer is enabled has UNPREDICTABLE effect according to
the BCM1250/BCM1125/BCM1125H User Manual. So stop the timer before
reprogramming.
This is a paranoia fix; no ill effects have been observed previously.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/kernel/cevt-bcm1480.c | 1 | ||||
| -rw-r--r-- | arch/mips/kernel/cevt-sb1250.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c index e54410e5a2c..0a57f86945f 100644 --- a/arch/mips/kernel/cevt-bcm1480.c +++ b/arch/mips/kernel/cevt-bcm1480.c @@ -75,6 +75,7 @@ static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd) cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); + __raw_writeq(0, cfg); __raw_writeq(delta - 1, init); __raw_writeq(M_SCD_TIMER_ENABLE, cfg); diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c index 8fbb0553768..63ac3ad462b 100644 --- a/arch/mips/kernel/cevt-sb1250.c +++ b/arch/mips/kernel/cevt-sb1250.c @@ -73,6 +73,7 @@ static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd) cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); + __raw_writeq(0, cfg); __raw_writeq(delta - 1, init); __raw_writeq(M_SCD_TIMER_ENABLE, cfg); |