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| author | Anoop P A <anoop.pa@gmail.com> | 2011-01-25 23:38:16 +0530 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-03-25 18:45:13 +0100 |
| commit | 3b042d0830463056a669a12362c940a94f7e3cd7 (patch) | |
| tree | 0a08c428c8bfe6f7530d676b7240c692ff3b7418 | |
| parent | 1685f3b158a244d4f6e205e67c84483fffcb2d9f (diff) | |
| download | linux-3.10-3b042d0830463056a669a12362c940a94f7e3cd7.tar.gz linux-3.10-3b042d0830463056a669a12362c940a94f7e3cd7.tar.bz2 linux-3.10-3b042d0830463056a669a12362c940a94f7e3cd7.zip | |
MIPS: MSP71xx: Set up MSP VPE1 timer.
VPE1 timer will be required for VSMP / SMTC.
[Ralf: Fixed a bunch of issues raised by checkpatch.]
Signed-off-by: Anoop P A <anoop.pa@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/2049/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/pmc-sierra/msp71xx/msp_time.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c index 01df84ce31e..8b42f307a7a 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_time.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c @@ -29,6 +29,7 @@ #include <linux/module.h> #include <linux/ptrace.h> +#include <asm/cevt-r4k.h> #include <asm/mipsregs.h> #include <asm/time.h> @@ -36,6 +37,12 @@ #include <msp_int.h> #include <msp_regs.h> +#define get_current_vpe() \ + ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE) + +static struct irqaction timer_vpe1; +static int tim_installed; + void __init plat_time_init(void) { char *endp, *s; @@ -83,5 +90,12 @@ void __init plat_time_init(void) unsigned int __cpuinit get_c0_compare_int(void) { - return MSP_INT_VPE0_TIMER; + /* MIPS_MT modes may want timer for second VPE */ + if ((get_current_vpe()) && !tim_installed) { + memcpy(&timer_vpe1, &c0_compare_irqaction, sizeof(timer_vpe1)); + setup_irq(MSP_INT_VPE1_TIMER, &timer_vpe1); + tim_installed++; + } + + return get_current_vpe() ? MSP_INT_VPE1_TIMER : MSP_INT_VPE0_TIMER; } |