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authorAlexander Duyck <alexander.h.duyck@intel.com>2010-11-16 19:26:59 -0800
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2010-11-16 19:26:59 -0800
commit32aa77a4fc06bd1116f83c25bf0389a3e9b80533 (patch)
tree7672d5a6b428f6dfcd5a3c42984435a059c78385
parentb953799ee29075afd30afe4c0fb65f278b088f69 (diff)
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ixgbe: change vector numbering so that queues end up on correct CPUs
This changes the numbering scheme slightly. Previously the ordering was coming out like this: Rx-2 Rx-1 Rx-0 TxRx-0 Which would drop two queues on CPU 0. This change makes it so that the ordering is like this: Rx-3 Rx-2 Rx-1 TxRx-0 This means that each CPU will have it's own Rx queue, and only CPU 0 will have the Tx queue. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 1d78b554b0e..5dde7d63c3a 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -2182,9 +2182,11 @@ static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
} else if (handler == &ixgbe_msix_clean_tx) {
sprintf(adapter->name[vector], "%s-%s-%d",
netdev->name, "tx", ti++);
- } else
+ } else {
sprintf(adapter->name[vector], "%s-%s-%d",
- netdev->name, "TxRx", vector);
+ netdev->name, "TxRx", ri++);
+ ti++;
+ }
err = request_irq(adapter->msix_entries[vector].vector,
handler, 0, adapter->name[vector],