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| author | Jack Morgenstein <jackm@dev.mellanox.co.il> | 2007-06-18 08:13:59 -0700 |
|---|---|---|
| committer | Roland Dreier <rolandd@cisco.com> | 2007-06-18 08:13:59 -0700 |
| commit | 082dee3216c99a838af40be403799f60bcea2e97 (patch) | |
| tree | 4741bc693e9eb882e5c72ab2d206cbe63e9dafaa | |
| parent | 54e95f8dcbd7d86f79b423e8d11053ec9a2d9946 (diff) | |
| download | linux-3.10-082dee3216c99a838af40be403799f60bcea2e97.tar.gz linux-3.10-082dee3216c99a838af40be403799f60bcea2e97.tar.bz2 linux-3.10-082dee3216c99a838af40be403799f60bcea2e97.zip | |
IB/mlx4: Handle buffer wraparound in __mlx4_ib_cq_clean()
When compacting CQ entries, we need to set the correct value of the
ownership bit in case the value is different between the index we copy
the CQE from and the index we copy it to.
Found by Ronni Zimmerman of Mellanox.
Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
| -rw-r--r-- | drivers/infiniband/hw/mlx4/cq.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/infiniband/hw/mlx4/cq.c b/drivers/infiniband/hw/mlx4/cq.c index e940521e9c8..660b27aecae 100644 --- a/drivers/infiniband/hw/mlx4/cq.c +++ b/drivers/infiniband/hw/mlx4/cq.c @@ -478,7 +478,8 @@ void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) { u32 prod_index; int nfreed = 0; - struct mlx4_cqe *cqe; + struct mlx4_cqe *cqe, *dest; + u8 owner_bit; /* * First we need to find the current producer index, so we @@ -501,9 +502,13 @@ void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); ++nfreed; - } else if (nfreed) - memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe), - cqe, sizeof *cqe); + } else if (nfreed) { + dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); + owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK; + memcpy(dest, cqe, sizeof *cqe); + dest->owner_sr_opcode = owner_bit | + (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); + } } if (nfreed) { |