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| author | Michael Hennerich <michael.hennerich@analog.com> | 2007-08-27 15:29:35 +0800 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-08-27 15:29:35 +0800 |
| commit | 07bdda02623d6d9078e45f6b6451bc3508878db1 (patch) | |
| tree | eb74a878abadfaccda5d5344d9317003c30aa96a | |
| parent | 3bebca2d20796dd3dc62c5d3e74148087c7ce5bd (diff) | |
| download | linux-3.10-07bdda02623d6d9078e45f6b6451bc3508878db1.tar.gz linux-3.10-07bdda02623d6d9078e45f6b6451bc3508878db1.tar.bz2 linux-3.10-07bdda02623d6d9078e45f6b6451bc3508878db1.zip | |
Blackfin arch: bug fixing restore mach dependent ASYNC memory size
Bug: When SMC921X driver is enabled, kernel boot crash on EZKIT548
http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3460
Fixed by restoring mach dependent ASYNC memory size CPLB coverage.
Once we have a more dynamic memory layout we should come up with a better
solution for these hard-coded values.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
| -rw-r--r-- | include/asm-blackfin/cplb.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index c9fc77684fb..df476689276 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -65,27 +65,33 @@ #define MAX_CPLBS (16 * 2) +#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ + ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) + /* * Number of required data CPLB switchtable entries * MEMSIZE / 4 (we mostly install 4M page size CPLBs * approx 16 for smaller 1MB page size CPLBs for allignment purposes * 1 for L1 Data Memory +* possibly 1 for L2 Data Memory * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO * 1 for ASYNC Memory */ -#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) +#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \ + + ASYNC_MEMORY_CPLB_COVERAGE) * 2) /* * Number of required instruction CPLB switchtable entries * MEMSIZE / 4 (we mostly install 4M page size CPLBs * approx 12 for smaller 1MB page size CPLBs for allignment purposes * 1 for L1 Instruction Memory +* possibly 1 for L2 Instruction Memory * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO */ -#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) +#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2) #define CPLB_ENABLE_ICACHE_P 0 |