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| author | Paul Walmsley <paul@pwsan.com> | 2011-02-25 15:39:27 -0700 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2011-03-07 20:02:13 -0700 |
| commit | 92618ff8b025419960e2e845983f0f49b0cb57a9 (patch) | |
| tree | ac747c8eafb7cdd6fee8399464cf79aa1b8e1f00 /arch/arm/mach-omap2/cm2xxx_3xxx.c | |
| parent | 0fd0c21be71293d8a54d9075b18b5a25a1868057 (diff) | |
| download | kernel-mfld-blackbay-92618ff8b025419960e2e845983f0f49b0cb57a9.tar.gz kernel-mfld-blackbay-92618ff8b025419960e2e845983f0f49b0cb57a9.tar.bz2 kernel-mfld-blackbay-92618ff8b025419960e2e845983f0f49b0cb57a9.zip | |
OMAP2xxx: clock: add clockfw autoidle support for APLLs
OMAP2xxx devices have two on-chip APLLs. These APLLs can
automatically enter idle when not in use. Connect the APLL autoidle
code to the clock code, so that the clock framework can handle this
process. As part of this patch, remove the code in mach-omap2/pm24xx.c
that previously handled APLL autoidle control.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Tested-by: Rajendra Nayak <rnayak@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/cm2xxx_3xxx.c')
| -rw-r--r-- | arch/arm/mach-omap2/cm2xxx_3xxx.c | 44 |
1 files changed, 43 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c index 6b0c7c85ef5..9d0dec806e9 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c @@ -25,10 +25,14 @@ #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" -/* CM_AUTOIDLE_PLL.AUTO_* bit values */ +/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */ #define DPLL_AUTOIDLE_DISABLE 0x0 #define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3 +/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */ +#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0 +#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3 + static const u8 cm_idlest_offs[] = { CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 }; @@ -154,6 +158,44 @@ void omap2xxx_cm_set_dpll_auto_low_power_stop(void) } /* + * APLL autoidle control + */ + +static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask) +{ + u32 v; + + v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); + v &= ~mask; + v |= m << __ffs(mask); + omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); +} + +void omap2xxx_cm_set_apll54_disable_autoidle(void) +{ + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, + OMAP24XX_AUTO_54M_MASK); +} + +void omap2xxx_cm_set_apll54_auto_low_power_stop(void) +{ + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, + OMAP24XX_AUTO_54M_MASK); +} + +void omap2xxx_cm_set_apll96_disable_autoidle(void) +{ + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, + OMAP24XX_AUTO_96M_MASK); +} + +void omap2xxx_cm_set_apll96_auto_low_power_stop(void) +{ + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, + OMAP24XX_AUTO_96M_MASK); +} + +/* * */ |