systeminfo: add initial risc-v support for cpu.archaccepted/tizen/unified/x/20240618.033354accepted/tizen/unified/dev/20240620.004736accepted/tizen/unified/20240618.195744

Change-Id: I212a894b66c7217c6b62af1d12af70a1dfc41611
Signed-off-by: Mateusz Bieganski <m.bieganski@samsung.com>

1 files changed, 25 insertions, 1 deletions

diff --git a/src/systeminfo/systeminfo_device_capability.cc b/src/systeminfo/systeminfo_device_capability.cc
index 47d9620e..2b8b9e40 100644
--- a/src/systeminfo/systeminfo_device_capability.cc
+++ b/src/systeminfo/systeminfo_device_capability.cc
@@ -57,6 +57,8 @@ const char* kPlatformCoreArmv8 = "armv8";
 const char* kPlatformCoreAarch64 = "aarch64";
 const char* kPlatformCoreX86 = "x86";
 const char* kPlatformCoreX86_64 = "x86_64";
+const char* kPlatformCoreRISCV64 = "riscv64";
+const char* kPlatformCoreRISCV32 = "riscv32";
 // core fpu arch
 const char* kPlatformCoreSse2 = "sse2";
 const char* kPlatformCoreSse3 = "sse3";
@@ -417,7 +419,29 @@ PlatformResult SystemInfoDeviceCapability::GetPlatfomCoreCpuArch(std::string* re
   bool bool_result = false;
   std::string arch = "";
 
-  PlatformResult ret = GetValueStringNative("tizen.org/feature/platform.core.cpu.arch", &arch);
+  PlatformResult ret = GetValueBoolNative("tizen.org/feature/platform.core.cpu.arch.riscv64", &bool_result);
+  if (ret.IsError()) {
+    LoggerE("GetValueBoolNative Error");
+    return ret;
+  }
+
+  if (bool_result) {
+    *return_value = std::string(kPlatformCoreRISCV64);
+    return PlatformResult(ErrorCode::NO_ERROR);
+  }
+
+  ret = GetValueBoolNative("tizen.org/feature/platform.core.cpu.arch.riscv32", &bool_result);
+  if (ret.IsError()) {
+    LoggerE("GetValueBoolNative Error");
+    return ret;
+  }
+
+  if (bool_result) {
+    *return_value = std::string(kPlatformCoreRISCV32);
+    return PlatformResult(ErrorCode::NO_ERROR);
+  }
+
+  ret = GetValueStringNative("tizen.org/feature/platform.core.cpu.arch", &arch);
   if (ret.IsError()) {
     LoggerE("GetValueStringNative Error");
   }